
Instruction Execution Timing
10-22
M68060 USER’S MANUAL
MOTOROLA
10.12 LEA, PEA, AND MOVEM EXECUTION TIMES
Table 10-20 indicates the number of clock cycles required for execution of the LEA, PEA,
and MOVEM instructions. The number of operand read and write cycles is shown in paren-
theses (r/w).
10.13 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 10-21 indicates the number of clock cycles for execution of the multiprecision instruc-
tions. The number of clock cycles includes the time to fetch both operands, perform the
operations, and store the results. The number of read and write cycles is shown in paren-
theses (r/w).
10.14 STATUS REGISTER, MOVES, AND MISCELLANEOUS
INSTRUCTION EXECUTION TIMES
execution of the status register, MOVES, and miscellaneous instructions. The number of
operand read and write cycles is shown in parentheses (r/w). Where indicated, the number
of clock cycles and r/w cycles must be added to those required for effective address calcu-
lation.
1 Add 2(1/0) cycles to the (bd,{An,PC},Xi*SF) time for a memory indirect address.
2 “n” is the number of registers being moved.
1 Where <ea>y,<ea>x is (Ay)+,(Ax)+ for CMPM and –(Ay),–(Ax) for all
other instructions.
Table 10-20. LEA, PEA, and MOVEM Instruction Execution Times
Instruction
(An)
+
–
(An)
(d16,An)
(d8,An,
Xi
SF)
(bd,An,
Xi
SF)1
(xxx).WL (d16,PC)
(d8,PC,
Xi
SF)
(bd,PC,
Xi
SF)1
LEA
1(0/0)
-
1(0/0)
2(0/0)
1(0/0)
2(0/0)
PEA
1(0/1)
-
2(0/1)
3(0/1)
1(0/1)
2(0/1)
MOVEM Mem->Reg
n2(n/
0)
n(n/
0)
-
n(n/0)
1+n(n/0) 2+n(n/0)
1+n(n/0)
n(n/0)
1+n(n/0) 2+n(n/0)
MOVEM Reg->Mem
n(0/n)
—
n(0/
n)
n(0/n)
1+n(0/n) 2+n(0/n)
1+n(0/n)
—
Table 10-21. Multiprecision Instruction Execution Times
Instruction
Size
op Dy,Dx
op
<ea>y,<ea>x1
ADDX
Byte, Word
1(0/0)
2(2/1)
“
Long
1(0/0)
2(2/1)
CMPM
Byte, Word
—
2(2/0)
“
Long
—
2(2/0)
SUBX
Byte, Word
1(0/0)
2(2/1)
“
Long
1(0/0)
2(2/1)
ABCD
Byte
1(0/0)
2(2/1)
SBCD
Byte
1(0/0)
2(2/1)