B-14
M68040 USER’S MANUAL
MOTOROLA
MC68EC040 REV2.3 (01/31/2000)
B.7.6 Output AC Timing Specifications (see Figures B-8* to B-12)
*Output timing is specied for a valid signal measured at the pin. Timing is specied driving an unterminated 30-
transmission line with a length characterized by a 2.5-nS one-way propagation delay. Buffer output impedance is
typically 30
; the buffer specications include approximately 5 nS for the signal to propagate the length of the
transmission line and back.
20 MHz
25 MHz
33 MHz
40 MHz
Unit
Num
Characteristic
Min
Max
Min
Max
Min
Max
Min
Max
11
BCLK to Address CIOUT, LOCK,
LOCKE,
R/W, SIZx, TLNx,TMx, TTx,
UPAx Valid
11.5
35
9
30
6.5
25
5.25
24
nS
12
BCLK to Output Invalid (Output
Hold)
11.5
—
9
—
6.5
—
5.25
—
nS
13
BCLK to TS Valid
11.5
35
9
30
6.5
25
5.25
24
nS
14
BCLK to TIP Valid
11.5
35
9
30
6.5
25
5.25
24
nS
18
BCLK to Data-Out Valid
11.5
37
9
32
6.5
27
5.25
26
nS
19
BCLK to Data-Out Invalid (Output
Hold)
11.5
—
9
—
6.5
—
5.25
—
nS
20
BCLK to Output Low Impedance
11.5
—
9
—
6.5
—
5.25
—
nS
21
BCLK to Data-Out High Imped-
ance
11.5
25
9
20
6.5
17
5.25
16
nS
38
BCLK to Address, CIOUT, LOCK,
LOCKE,
R/W, SIZx, TS, TLNx, TMx,
TTx, UPAx High
Impedance
11.5
23
9
18
6.5
15
5.25
14
nS
39
BCLK to BB, TA, TIP High Imped-
ance
23
33
19
28
14
25
11.5
22
nS
40
BCLK to BR, BB Valid
11.5
35
9
30
6.5
23
5.25
14
nS
43
BCLK to MI Valid
11.5
35
9
30
6.5
25
5.25
24
nS
48
BCLK to TA Valid
11.5
35
9
30
6.5
25
5.25
24
nS
50
BCLK to IPEND, PSTx, RSTO
Valid
11.5
35
9
30
6.5
25
5.25
24
nS
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Freescale Semiconductor, Inc.
For More Information On This Product,
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