MOTOROLA
M68020 USER’S MANUAL
8- 17
8.2.4 Calculate Immediate Effective Address
The calculate immediate effective address table indicates the number of clock periods
needed for the processor to fetch the immediate source operand and calculate the
specified destination effective address. Fetch time is only included for the first level of
indirection on memory indirect addressing modes. The total number of clock cycles is
outside the parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Address Mode
Best Case
Cache Case
Worst Case
#<data >.W,Dn
0(0/0/0)
2(0/0/0)
3(0/1/0)
#<data >.L,Dn
1(0/0/0)
4(0/0/0)
5(0/1/0)
#<data >.W,(An)
0(0/0/0)
2(0/0/0)
3(0/1/0)
#<data >.L,(An)
1(0/0/0)
4(0/0/0)
5(0/1/0)
#<data >.W,(An)+
2(0/0/0)
4(0/0/0)
5(0/1/0)
#<data >.L,(An)+
3(0/0/0)
6(0/0/0)
7(0/1/0)
#<data >.W,(bd,An)
1(0/0/0)
4(0/0/0)
5(0/1/0)
#<data >.L,(bd,An)
3(0/0/0)
6(0/0/0)
8(0/2/0)
#<data >.W,xxx.W
1(0/0/0)
4(0/0/0)
5(0/1/0)
#<data >.L,xxx.W
3(0/0/0)
6(0/0/0)
8(0/2/0)
#<data >.W,xxx.L
2(0/0/0)
4(0/0/0)
6(0/2/0)
#<data >.L,xxx.L
3(0/0/0)
8(0/0/0)
10(0/2/0)
#<data >.W,(d8,An,Xn) or (d8,PC,Xn)
0(0/0/0)
6(0/0/0)
8(0/2/0)
#<data >.L,(d8,An,Xn) or (d8,PC,Xn)
2(0/0/0)
8(0/0/0)
10(0/2/0)
#<data >.W,(d16,An,Xn) or (d16,PC,Xn)
3(0/0/0)
8(0/0/0)
10(0/2/0)
#<data >.L,(d16,An,Xn) or (d16,PC,Xn)
4(0/0/0)
10(0/0/0)
12(0/2/0)
#<data >.W,(B)
3(0/0/0)
8(0/0/0)
10(0/1/0)
#<data >.L,(B)
4(0/0/0)
10(0/0/0)
12(0/2/0)
#<data >.W,(bd,PC)
9(0/0/0)
14(0/0/0)
18(0/3/0)
#<data >.L,(bd,PC)
10(0/0/0)
16(0/0/0)
20(0/3/0)
#<data >.W,(d16,B)
5(0/0/0)
10(0/0/0)
13(0/2/0)
#<data >.L,(d16,B)
6(0/0/0)
12(0/0/0)
15(0/2/0)
#<data >.W,(d32,B)
9(0/0/0)
14(0/0/0)
18(0/2/0)
#<data >.L,(d32,B)
10(0/0/0)
16(0/0/0)
20(0/3/0)
#<data >.W,([B],I)
8(1/0/0)
13(1/0/0)
15(1/2/0)
#<data >.L,([B],I)
9(1/0/0)
15(1/0/0)
17(1/2/0)
#<data >.W,([B],I,d 16)
10(1/0/0)
15(1/0/0)
18(1/2/0)
#<data >.L,([B],I,d16)
11(1/0/0)
17(1/0/0)
20(1/2/0)
#<data >.W,([B],I,d 32)
10(1/0/0)
15(1/0/0)
19(1/2/0)
#<data >.L,([d16,B],I,d32)
11(1/0/0)
17(1/0/0)
21(1/3/0)
#<data >.W,([d 16,B],I)
10(1/0/0)
15(1/0/0)
18(1/2/0)
#<data >.L,([d16,B],I)
11(1/0/0)
17(1/0/0)
20(1/2/0)
#<data >.W,([d 16,B],I,d16)
12(1/0/0)
17(1/0/0)
21(1/2/0)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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