
Register Descriptions
568347 Technical Data
105
Preliminary
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register
reads $401D.
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can
have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups
disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a
peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see
deactivate the internal pull-up resistor.
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1 Reserved—Bit 1
5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
PWMA1—Bit 14
This bit controls the pull-up resistors on the FAULTA3 pin.
6.5.6.3
CAN—Bit 13
This bit controls the pull-up resistors on the CAN_RX pin.
6.5.6.4
EMI_MODE—Bit 12
This bit controls the pull-up resistors on the EMI_MODE pin.
6.5.6.5
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
6.5.6.6
IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA and IRQB pins.
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
0
1
0
1
Write
RESET
0
1
0000
0
1
0
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT
PWMB
PWMA0
0
CTRL
0
JTAG
00
0
Write
RESET
00
0