參數(shù)資料
型號: MC56F8345MFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8345 16-bit Hybrid Controller
中文描述: 0-BIT, 240 MHz, OTHER DSP, PQFP128
封裝: 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
文件頁數(shù): 92/148頁
文件大?。?/td> 1420K
代理商: MC56F8345MFG60
92
56F8345 Technical Data
Preliminary
5.6.30
ITCN Control Register (ICTL)
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1 Interrupt (INT)—Bit 15
This
read-only
bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
These
read-only
bits reflect the state of the new interrupt priority level bits being presented to the
56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core
jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service
routine can read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This
read-only
field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken.
This field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service
routine can read it.
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3
This
read-only
bit reflects the state of the external IRQB pin.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This
read-only
bit reflects the state of the external IRQA pin.
Base + $1D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
INT
IPIC
VAB
INT_DIS
1
IRQB STATE
IRQA STATE
IRQB
EDG
IRQA
EDG
Write
RESET
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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