參數(shù)資料
      型號: MC56F8345MFG60
      廠商: MOTOROLA INC
      元件分類: 數(shù)字信號處理
      英文描述: 56F8345 16-bit Hybrid Controller
      中文描述: 0-BIT, 240 MHz, OTHER DSP, PQFP128
      封裝: 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
      文件頁數(shù): 34/148頁
      文件大?。?/td> 1420K
      代理商: MC56F8345MFG60
      34
      56F8345 Technical Data
      Preliminary
      1. Cannot be used since MA = EXTBOOT = 0 and the EMI is not available; information in shaded areas not applicable to
      56F8345.
      2. This mode provides maximum compatibility with 56F80x parts while operating externally.
      3.
      “EMI_MODE = 0”, EMI_MODE pin is tied to ground at boot up.
      4. “EMI_MODE = 1”, EMI_MODE pin is tied to V
      DD
      at boot up.
      5. Not accessible in this part, since the EMI is not fully pinned out in this package; information in shaded areas not applicable
      to 56F8345.
      4.3 Interrupt Vector Table
      Table 4-5
      provides the reset and interrupt priority structure, including on-chip peripherals. The
      table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the
      table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some
      control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
      a selected priority level, the lowest vector number has the highest priority.
      The location of the vector table is determined by the Vector Base Address (VBA) register. Please
      see
      Section 5.6.11 Vector Base Address Register (VBA)
      for the reset value of the VBA.
      In some configurations, the reset address and COP reset address will correspond to vector 0 and 1
      of the interrupt vector table. In these instances, the first two locations in the vector table must
      contain branch or JMP instructions. All other entries must contain JSR
      instructions.
      Table 4-4 Program Memory Map at Reset
      Begin/End
      Address
      Mode 0 (MA = 0)
      Mode 1
      1
      (MA = 1)
      Internal Boot
      External Boot
      Internal Boot
      16-Bit External Address Bus
      EMI_MODE = 0
      2, 3
      16-Bit External Address Bus
      EMI_MODE = 1
      4
      20-Bit External Address Bus
      P:$1F FFFF
      P:$10 0000
      External Program Memory
      5
      External Program Memory
      5
      External Program Memory
      5
      P:$0F FFFF
      P:$03 0000
      External Program RAM
      5
      COP Reset Address = 02 0002
      Boot Location = 02 0000
      P:$02 FFFF
      P:$02 F800
      On-Chip Program RAM
      4KB
      On-Chip Program RAM
      4KB
      P:$02 F7FF
      P:$02 1000
      Reserved
      116KB
      P:$02 0FFF
      P:$02 0000
      Boot Flash
      8KB
      COP Reset Address = 02 0002
      Boot Location = 02 0000
      Boot Flash
      8KB
      (Not Used for Boot in this Mode)
      P:$01 FFFF
      P:$01 0000
      External Program RAM
      5
      Internal Program Flash
      128KB
      P:$00 FFFF
      P:$00 0000
      Internal Program Flash
      128KB
      External Program RAM
      5
      COP Reset Address = 00 0002
      Boot Location = 00 0000
      F
      Freescale Semiconductor, Inc.
      For More Information On This Product,
      Go to: www.freescale.com
      n
      .
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