參數(shù)資料
型號(hào): MC56F8257MLH
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 53/88頁(yè)
文件大?。?/td> 0K
描述: DSC 64K FLASH 60MHZ 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 管件
Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
57
Figure 16 shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 16. Signal States
7.11
Enhanced Flex PWM Characteristics
7.12
Flash Memory Characteristics
7.13
External Clock Operation Timing
Table 27. Enhanced Flex PWM Timing Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
NanoEdge Placement (NEP) step size1 2 3
1 Required: IP bus clock is between 50 MHz and ~60 Mhz in NanoEdge Placement mode.
2 NanoEdge Placement step size is a function of clock frequency only. Temperature and voltage variations do not affect
NanoEdge Placement step size.
3 In NanoEdge Placement mode, the minimum pulse edge-to-edge cannot be less than 4 PWM clock cycles.
521
ps
Delay for fault input activating to PWM output deactivated
1
ns
Table 28. Flash Timing Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Program time1
1 Additional overhead is part of the programming sequence. Refer to the device’s reference manual for details.
tprog
20
40
μs
Erase time 2
2 Specifies page erase time. There are 1024 bytes per page in the program flash memory.
terase
20
ms
Mass erase time
tme
100
ms
Table 29. External Clock Operation Timing Requirements1
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
fosc
——
120
MHz
Clock pulse width3
tPW
6.25
ns
Data Invalid State
Data1
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
Data2 Valid
Data
Three-stated
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