參數(shù)資料
型號: MC56F8257MLH
廠商: Freescale Semiconductor
文件頁數(shù): 24/88頁
文件大?。?/td> 0K
描述: DSC 64K FLASH 60MHZ 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Memory Maps
Freescale Semiconductor
30
4.2
Program Map
The MC56F825x/MC56F824x series provide up to 64 KB on-chip flash memory. It primarily accesses through the program
memory buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB.
Data can be read from and written to the program memory space through the primary data memory buses: CDBW for data write
and CDBR for data read. Access time for accessing the program memory space over the data memory buses is longer than for
accessing data memory space. The special MOVE instructions are provided to support these accesses. The benefit is that
non-time-critical constants or tables can be stored and accessed in program memory.
The program memory map appears in Table 7, Table 8, and Table 9, depending on the device.
Table 6. Chip Memory Configurations
On-Chip Memory
56F8245
56F8246
56F8247
56F8255
56F8256
56F8357
Use Restrictions
Program Flash
(PFLASH)
24K x 16
or
48 KB
24K x 16
or
48 KB
32K x 16
or
64 KB
Erase/program via flash interface unit and word writes to CDBW
Unified RAM
(RAM)
3K x 16
or
6 KB
4K x 16
or
8KB
4K x 16
or
8KB
Usable by the program and data memory spaces
Table 7. Program Memory Map1 for 56F8255/56/57 at Reset
1 All addresses are 16-bit word addresses.
Begin/End Address
Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 8FFF
P: 0x00 8000
On-chip RAM2: 8 KB
2 This RAM is shared with data space starting at address X: 0x00 0000. See Figure 6.
P: 0x00 7FFF
P: 0x00 0000
Internal program flash: 64 KB
Interrupt vector table locates from 0x00 0000 to 0x00 0085
COP reset address = 0x00 0002
Boot location = 0x00 0000
Table 8. Program Memory Map1 for 56F82447 at Reset
Begin/End Address
Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 8FFF
P: 0x00 8000
On-chip RAM2: 8 KB
P: 0x00 7FFF
P: 0x00 2000
Internal program flash: 48 KB
Interrupt vector table locates from 0x00 2000 to 0x00 2085
COP reset address = 0x00 2002
Boot location = 0x00 2000
P: 0x00 2000
P: 0x00 0000
RESERVED
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