Signal/Connection Descriptions
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
15
3.2
Pin Assignment
Figure 3 shows the pin assignments of the 56F8245 and 56F8255’s 44-pin low-profile quad flat pack (44LQFP).
Figure 4 shows
the pin assignments of the 56F8246 and 56F8256’s 48-pin low-profile quad flat pack (48LQFP).
Figure 5 shows the pin
assignments of the 56F8247 and 56F8257’s 64-pin low-profile quad flat pack (64LQFP).
NOTE
The CANRX and CANTX signals of the MSCAN module are not available on the
MC56F824x devices.
Figure 3. Top View: 56F8245 and 56F8255 44-Pin LQFP Package
GPIOD2/TCK
GPIOD4/RESET
GPIOC0/XTAL/CLKIN
GPIOC1/EXTAL
GPIOC2/TXD0/TB0/XB_IN2/CLKO
GPIOC3/TA0/CMPA_O/RXD0
GPIOC4/TA1/CMPB_O
GPIOA0/ANA0/CMPA_P2/CMPC_O
GPIOA1/ANA1/CMPA_M0
GPIOA2/ANA2/VREFHA/CMPA_M1
GPIOA3/ANA3/VREFLA/CMPA_M2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
G
P
IO
C5
/D
A
C
O/
XB
_
IN7
VDD
A
VSS
A
G
P
IO
B0
/A
N
B
0/
CMPB_P
2
G
P
IO
B1
/A
NB
1
/CM
P
B
_
M
0
VCA
P
GPIOB
2
/A
NB2/VREFHB/CMPC_P
2
GPI
O
B
3
/A
NB3/
VREF
LB
/CMP
C_
M0
VS
S
GPI
O
C6
/T
A2
/X
B_I
N
3/CMP
_
REF
GP
IO
C7/S
S
/T
XD0
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
GP
IO
D0
/TD
I
GP
IO
D3
/TM
S
GP
IO
D1
/TD
O
VS
S
VD
D
VC
A
P
GP
IO
C1
5
/S
C
L
0
/X
B
_
OU
T1
GP
IO
C1
4
/S
D
A
0
/X
B_
O
U
T0
GP
IO
E
5
/P
W
M
2A
/X
B
_
IN3
GP
IO
E
4
/P
W
M
2B
/X
B
_
IN2
G
P
IO
C13/
T
A
3/
XB
_IN6
GPIOE3/PWM1A
GPIOE2/PWM1B
GPIOE1/PWM0A
GPIOE0/PWM0B
VDD
VSS
GPIOC12/CANRX0/SDA1/RXD1
GPIOC11/CANTX0/SCL1/TXD1
GPIOC10/MOSI/XB_IN5/MISO
GPIOC9/SCLK/XB_IN4
GPIOC8/MISO/RXD0
