參數(shù)資料
型號: MC56F8025VLD
廠商: Freescale Semiconductor
文件頁數(shù): 37/161頁
文件大?。?/td> 0K
描述: IC DSP 16BIT DUAL HARV 44-LQFP
標準包裝: 800
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 托盤
Phase Locked Loop Timing
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
131
10.6 Phase Locked Loop Timing
Table 10-11 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
is optimized for 8MHz input.
fosc
48
MHz
Internal reference relaxation oscillator frequency for the PLL
frosc
—8—
MHz
PLL output frequency2 (24 x reference frequency)
2. The core system clock will operate at 1/6 of the PLL output frequency.
fop
96
192
MHz
PLL lock time3
3. This is the time required after the PLL is enabled to ensure reliable operation.
tplls
—40
100
s
Accumulated jitter using an 8MHz external crystal as the PLL source4
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
and using an 8MHz oscillator frequency.
JA
0.37
%
Cycle-to-cycle jitter
tjitterpll
—350
ps
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