參數資料
型號: MC56F8025VLD
廠商: Freescale Semiconductor
文件頁數: 159/161頁
文件大?。?/td> 0K
描述: IC DSP 16BIT DUAL HARV 44-LQFP
標準包裝: 800
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數: 35
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數據轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 托盤
Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
97
Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control
In some cases, the user can choose peripheral function between several I/O, each of which have the option
to be programmed to control a specific peripheral function. If the user wishes to use that function, only one
of these I/O must be configured to control that peripheral function. If more than one I/O is configured to
control the peripheral function, the peripheral output signal will fan out to each I/O, but the peripheral input
signal will be the logical OR and AND of all the I/O signals.
Complete lists of I/O muxings are provided in Table 2-3.
The GPSn setting can be altered during normal operation, but a delay must be inserted between the time
when one function is disabled and another function is enabled.
Note:
After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin.
Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
6.3.16.1
Reserved—Bits 15–13
This bit field is reserved. Each bit must be set to 0.
6.3.16.2
Configure GPIOA6 (GPS_A6)—Bit 12
This field selects the alternate function for GPIOA6.
0 = FAULT0 - PWM FAULT0 Input (default)
1 = TA0 - Timer A0
6.3.16.3
Configure GPIOA5 (GPS_A5)—Bits 11–10
This field selects the alternate function for GPIOA5.
00 = PWM5 - PWM5 (default)
Base + $13
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
GPS_A6
GPS_A5
GPS_A4
0
Write
RESET
0
00000000
0000
GPIOA6_PEREN
Register
GPIOA6
GPIOA6 pin
SIM_GPSA0
Register
PWM
FAULT0
Timer A0
0
1
0
1
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