參數(shù)資料
型號： MC56F8013VFAER2
廠商： Freescale Semiconductor
文件頁數(shù)： 46/126頁
文件大小： 0K
描述： IC DIGITAL SIGNAL CTLR 32-LQFP
標準包裝： 2,000
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 帶卷 (TR)
56F8013/56F8011 Data Sheet, Rev. 12
26
Freescale Semiconductor
Part 3 OCCS
3.1 Overview
This module provides the system clock, which is used to generate the various chip clocks. This module
also produces the oscillator clock plus the ADC clock and high-speed peripheral clock.
The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run
56F801X family parts at user-selectable frequencies up to 32MHz.
3.2 Features
The On-Chip Clock Synthesis (OCCS) module interfaces to the oscillator and PLL. The OCCS module
features:
Internal relaxation oscillator
Ability to power down the internal relaxation oscillator
Ability to put the internal relaxation oscillator into a standby mode
3-bit postscaler provides control for the PLL output
Ability to power down the internal PLL
Provides 2X system clock, which operates at twice the system clock, to the System Integration Model (SIM)
that is used to generate the various device clocks
Provides 3X system clock, which operates at three times the system clock, to PWM and Timer
Safety shutdown feature is available in the event that the PLL reference clock is lost
Can be driven from an external clock source
The clock generation module provides the programming interface for both the PLL and internal relaxation
oscillator.
3.3 Operating Modes
In 56F801X family parts, either an internal oscillator or an external frequency source can be used to
provide a reference clock to the SIM.
The 2X system clock source output from the OCCS can be described by one of the following equations:
2X system frequency = oscillator frequency
2X system frequency = (oscillator frequency X 8) / (postscaler)
where:
postscaler = 1, 2, 4, 8, 16, or 32 PLL output divider
The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle
in the system clock output.
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MC56F8013MFAE IC DIGITAL SIGNAL CTLR 32-LQFP
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