參數(shù)資料
型號(hào): MC56F8002MWL
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PDSO28
封裝: 7.50 X 18 MM, ROHS COMPLIANT, MS-013AE, SOIC-28
文件頁(yè)數(shù): 66/106頁(yè)
文件大小: 1215K
代理商: MC56F8002MWL
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor
62
Figure 31. RXD Pulse Width
Figure 32. TXD Pulse Width
8.13.3
Inter-Integrated Circuit Interface (I2C) Timing
Table 31. I2C Timing
Characteristic
Symbol
Standard Mode
Unit
Minimum
Maximum
SCL Clock Frequency
fSCL
0100
MHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
tHD; STA
4.0
s
LOW period of the SCL clock
tLOW
4.7
s
HIGH period of the SCL clock
tHIGH
4.0
s
Set-up time for a repeated START condition
tSU; STA
4.7
s
Data hold time for I2C bus devices
tHD; DAT
01
1 The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.452
2 The maximum t
HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
s
Data set-up time
tSU; DAT
250
ns
Rise time of SDA and SCL signals
tr
1000
ns
Fall time of SDA and SCL signals
tf
—300
ns
Set-up time for STOP condition
tSU; STO
4.0
s
Bus free time between STOP and START condition
tBUF
4.7
s
Pulse width of spikes that must be suppressed by the input filter
tSP
N/A
ns
RXDPW
RXD
SCI receive
data pin
(Input)
TXDPW
TXD
SCI receive
data pin
(Input)
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