OPERATIONAL MODES Figure 11. Reset and WDOG" />
參數資料
型號： MC33889DPEGR2
廠商： Freescale Semiconductor
文件頁數： 24/59頁
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/CAN 28SOIC
標準包裝： 1,000
系列： *
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
33889
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11. Reset and WDOG Function Diagram
DEBUG MODE APPLICATION HARDWARE AND SOFTWARE DEBUG WITH THE SBC.
When the SBC is mounted on the same printed circuit board as the micro controller, it supplies both application software and
the SBC with a dedicated routine that must be debugged. The following features allow the user to debug the software by disabling
the SBC internal software watchdog timer.
DEVICE POWER UP, RESET PIN CONNECTED TO VDD1
At SBC power up, the VDD1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
every 350 ms. In order to allow software debugging and avoid an MCU reset, the Reset pin can be connected directly to VDD1
by a jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY DEBUG AND
STOP DEBUG)
The software watchdog can be disabled through the SPI. In order to avoid unwanted watchdog disables, and to limit the risk
of disabling the watchdog during an SBC normal operation, the watchdog disable has to be performed with the following
sequence:
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode)
Step 3) Write to the TIM1 register to allow the SBC to enter Normal mode
Step 4) Write to the MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000)
Step 5) Write to the MCR register normal debug (0001 x101), stand-by debug (0001 x110), or Stop debug (0001 x111)
While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and
hardware debugging.
Step 6) To leave the debug mode, write 0000 to the MCR register.
To avoid entering the debug mode after a power up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR.
Figure 12 illustrates entering the debug mode.
RESET
WDOG
VDD1
SPI
SPI CS
Watchdog timeout
Watchdog register addressed
Watchdog
period
W/D clear
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