DYNAMIC ELECTRICAL CHARACTERISTICS Delay bet" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC33889DPEGR2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 11/59闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC SYSTEM BASE W/CAN 28SOIC
妯欐簴鍖呰锛� 1,000
绯诲垪锛� *
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
33889
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Delay between SPI and 鈥淐AN normal mode鈥�
SBC Normal mode (24)
tS-CANN
-
10
s
Delay between SPI and 鈥淐AN sleep mode鈥�
SBC Normal mode (24)
tS-CANS
-
10
s
Delay between CS wake-up (CS low to high) and SBC normal
request mode (VDD1 on & reset high)
SBC in Stop mode
tW-CS
15
40
90
s
Delay between CS wake-up (CS low to high) and first accepted
SPI command
SBC in Stop mode
tW-SPI
90
-
s
Delay between INT pulse and 1st SPI command accepted
In Stop mode after wake-up
tS-1STSPI
20
-
s
Delay between two SPI messages addressing the same
register
For 33889D only
t2SPI
25
-
s
INPUT PINS (L0 AND L1)
Wake-up Filter Time (enable/disable option on L0 input)
(If filter enabled)
tWUF
8.0
20
38
s
PIN AC CHARACTERISTICS (CANH, CANL, RX, TX)
CANL and CANH Slew Rates (25% to 75% CAN signal). (25)
Recessive to Dominant state
Dominant to Recessive state
tSLDR
2.0
-
8.0
9.0
V/
s
Propagation Delay
TX to RX Low. -40 < T
25掳C. (26)
TX to RX Low. 25 < T < 125掳C. (26)
tONRX
-
1.2
1.1
1.6
1.8
s
Propagation Delay TX to RX High. (26)
tOFFRX
-
1.8
2.2
s
Notes
24.
Guaranteed by design
25.
Dominant to recessive slew rate is dependant upon the bus load characteristics.
26.
AC Characteristics measured according to schematic Figure 5
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40 to 150 掳C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25掳C under nominal conditions, unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
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