參數(shù)資料
型號: MC33889
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: System Basis Chip (SBC) with Low Speed Fault Tolerant CAN Interface
中文描述: 帶有低速CAN的精簡版系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 26/30頁
文件大?。?/td> 464K
代理商: MC33889
PC33889
26
PC33889
Control bits:
.
Status bits:
7.2.6
TIM registers
Description: This register is splitted into 2 sub registers, TIM1 and TIM2.
TIM1 controls the watchdog timing selection as well as the window or time out option. TIM1 is selected when bit D3 is 0.
TIM2 is used to define the timing for the cyclic sense and forced wake up function. TIM2 is selected when bit D3 is 1.
No read operation is allowed for registers TIM1 and TIM2
7.2.7
TIM register
Description.
LCTR3
LCTR2
LCTR1
LCTR0
L0 configuration
L1 configuration
X
X
0
0
inputs disabled
X
X
0
1
high level sensitive
X
X
1
0
low level sensitive
X
X
1
1
both level sensitive
0
0
X
X
inputs disabled
0
1
X
X
high level sensitive
1
0
X
X
low level sensitive
1
1
X
X
both level sensitive
Table 7-11.
L0WUb
L0WUa
FDIS bit in
CAN register
Description
0
0
0
No wake up occurred at L0 (sleep or stop mode).
Low level state on L0 (standby or normal mode)
1
1
0
Wake up occurred at L0 (sleep or stop mode).
High level state on L0 (standby or normal mode)
0
1
1
Wake up occurred at L0 (sleep or stop mode with L0 filter disable). WUR
must be set to xx00 before sleep or stop mode.
L1WUb
L1WUa
Description
0
0
No wake up occurred at L1 (sleep or stop mode).
Low level state on L1 (standby or normal mode)
1
1
Wake up occurred at L1 (sleep or stop mode).
High level state on L1 (standby or normal mode)
TIM1
D3
D2
D1
D0
$101b
W
0
WDW
WDT1
WDT0
R
Table 7-12.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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