LOGIC COMMANDS AND REGISTERS NOTE: For SPI " />
參數(shù)資料
型號(hào)： MC33742SDWR2
廠商： Freescale Semiconductor
文件頁數(shù)： 42/71頁
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/LIN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
配用： KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
NOTE: For SPI Operation
In case a low pulse is asserted by the device on the RST output pin during a SPI message,
the SPI message can be corrupted. An RST low pulse is asserted in 2 cases:
Case 1: W/D refresh issue: The MCU does not perform the SPI watchdog refresh command
before the expiration of the timeout (in Normal mode or Normal Request mode and if the
“Timeout watchdog” option is selected), or the SPI watchdog refresh command is performed
in the closed window (in Normal mode and if “Window watchdog” option is selected).
Case 2: VDD undervoltage condition: VDD falls below the VDD undervoltage threshold.
Message corruption means that the targeted register address can be changed, and another
register is written. Table 15 shows the various cases and impacts on SPI register address:
Four registers can be corrupted: MCR, RCR, CAN, and IOR registers. As examples:
write to CAN register can end up as write to MCR register, or
write to TIM1 register can end up as write to RCR register
To avoid the previously described behavior, it is recommended to write into the MCR, RCR,
CAN, and IOR registers with the expected configuration, after each RST assertion.
In the application, a RST low pulse leads to an MCU reset and a software restart. By
applying this recommendation, all registers will be written with the expected configuration.
IOR
$011
HS (high side switch) control in Normal
and Standby mode
HS over-temperature bit, VSUP, and V2
LOW status
WUR
$100
Control of wake-up input polarity
Wake-up input and real time Lx input
state
TIM
$101
TIM1: Watchdog timing control, Watch-
dog Window (WDW) or Watchdog Tim-
eout (WTO) mode
TIM2: Cyclic Sense and Forced Wake-
up timing selection
CANL and TXD failure reporting
LPC
$110
Control HS periodic activation in Sleep
and Stop modes, Forced Wake-up mode
activation, CAN-INT mode selection
CANH and RXD failure reporting
INTR
$111
Enable or Disable of Interrupts
Interrupt source
Table 15. Possible Corrupted Registers In Case of RST Pulse During SPI Communication
Resulting Written register
Register
MCR
RCR
CAN
IOR
Address
$000
$001
$010
$011
Target
written
register
Register
Address
CAN
$010
X
IOR
$011
X
WUR
$100
X
TIM1/2
$101
X
LPC
$110
X
INTR
$111
X
Table 14. List of Registers
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