LOGIC COMMANDS AND REGISTERS TIMING REGISTE" />
參數(shù)資料
型號(hào)： MC33742SDW
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 48/71頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/LIN 28-SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 自動(dòng)
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
安裝類(lèi)型： 表面貼裝
配用： KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN
Analog Integrated Circuit Device Data
52
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
TIMING REGISTER (TIM1/2)
Tables 31 through 35 contain the Timing Register information. The TIM register is composed of two sub registers:
TIM1—Controls the watchdog timing selection as well as either the watchdog window or the watchdog timeout option
(Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 31). Watchdog timing characteristics are
described in Table 32.
TIM2—Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on
or off. TIM2 is selected when bit D3 is 1 (Table 33). Figure 30, page 54, describes HS operation when cyclic sense is selected
Cyclic sense timing characteristics are described in Table 35, page 54.
Both subregisters also report the CANL and TXD diagnostics.
0
x
–
Inputs Disabled
0
1
x
High Level Sensitive
1
0
x
Low Level Sensitive
1
x
Both Level Sensitive
x = Don’t care.
Table 30. Wake-up Register Status Bits (62)
Name
Logic
Description
L3WU
0 or 1
If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has
occurred.
When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW
or HIGH) (0 = Lx LOW, 1 = Lx HIGH)
L2WU
0 or 1
L1WU
0 or 1
L0WU
0 or 1
Notes
62.
WUR status bits have two functions. After SBC wake-up, they indicate the wake-up source; for example, L2WU set at logic [1] if wake-
up source is L2 input. After SBC wake-up and once the WUR register has been read, status bits indicate the real-time state of the Lx
inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog timeout occurs before the
first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode.
Table 31. TIM1 Timing and CANL Failure Diagnostic Register
TIM1
R/W
D3
D2
D1
D0
$101b
W
0
WDW
WDT1
WDT0
R
CANL2VDD
CANL2BAT
CANL2GND
TXPD
Reset Value
–
0
Reset Condition (Write)(63)
–
POR, RESET
Notes
63.
See Table 13, page 46, for definitions of reset conditions.
Table 29. Wake-up Register Control Bits (continued)
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