THERMAL ADDENDUM (REV 2.0) ADDITIONAL DOCUMENT" />
參數(shù)資料
型號(hào): MC33742EP
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 63/71頁(yè)
文件大小: 0K
描述: IC SYSTEM BASE W/CAN 48-QFN
標(biāo)準(zhǔn)包裝: 260
應(yīng)用: 自動(dòng)
接口: SPI
電源電壓: 5.5 V ~ 18 V
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 托盤
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
66
Freescale Semiconductor
33742
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33742
technical datasheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application, and packaging information is
provided in the data sheet.
Packaging and Thermal Considerations
The MC33742 is offered in a 28 pin SOICW exposed pad, single die
package. There is a single heat source (P), a single junction temperature
(TJ), and thermal resistance (RJA).
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology
is not meant to and will not predict the performance of a package in an
application-specific environment. Stated values were obtained by
measurement and simulation according to the standards listed below.
Standards
Table 44. Thermal Performance Comparison
Thermal Resistance
[
C/W]
41
10
68
RJC
220
Notes:
1.
Per JEDEC JESD51-2 at natural convection, still air
condition.
2.
2s2p thermal test board per JEDEC JESD51-7.
3.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
4.
Single layer thermal test board per JEDEC JESD51-3.
5.
Thermal resistance between the die junction and the
package top surface; cold plate attached to the package top
surface and remaining surfaces insulated.
28-PIN SOICW
33742SOICW
EG SUFFIX (PB-FREE)
98ASB42345B
28-PIN SOICW
Note For package dimensions, refer to
98ASB42345B.
TJ
=
RJA
.
P
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