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| 型號： | MC33742DWR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 51/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYSTEM BASE W/LIN 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 自動 |
| 接口： | SPI |
| 電源電壓： | 5.5 V ~ 18 V |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
| 配用： | KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
55
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 36. Low Power Control Register
LPC
R/W
D3
D2
D1
D0
$110b
W
LX2HS
FWU
CAN-INT
HSAUTO
R
CANH2VDD
CANH2BAT
CANH2GND
RXPR
Reset Value
–
0
Reset Condition (Write)(65)
–
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
Notes
65.
See Table 13, page 46, for definitions of reset conditions.
Table 37. LX2HS Control Bits
Logic
Wake-up Inputs Supplied by HS
0
No.
1
Yes. Lx inputs sensed at sampling point.
Table 38. HSAUTO Control Bits
Logic
Auto-timing HS in Sleep and Stop modes
0
OFF.
1
ON, HS Cyclic, period defined in TIM2 subregister.
Table 39. CAN-INT Control Bits
Logic(66)
Description
0
Interrupt as soon as CAN bus failure detected.
1
Interrupt when CAN bus failure detected and fully identified.
Notes
66.
If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by
SPI (refer to CAN Register (CAN) on page 49). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared
automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not
allow clearing the CAN-UF bit.
Table 40. LPC Status Bits
Name
Logic
Failure Description
CANH2VDD
0
No CANH short to VDD.
1
CANH short to VDD.
CANH2BAT
0
No CANH short to VSUP.
1
CANH short to VSUP.
CANH2GND
0
No CANH short to GND.
1
CANH short to GND.
RXPR
0
No RXD permanent recessive.
1
RXD permanent recessive.
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