LOGIC COMMANDS AND REGISTERS LOGIC COMMA" />
參數(shù)資料
型號(hào)： MC33742DWR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 41/71頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/LIN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
配用： KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
DATA FORMAT DESCRIPTION
Figure 27 illustrates an 8-bit byte corresponding to the 8 bits in a SPI register. The first three bits are used to identify the
internal SBC register address. Bit 4 is a read/write bit. The last four bits are data sent from the MCU to the SBC or read back
from the 33742 to the MCU.
The state of the MISO has no significance during the write operation. However, during a read operation the final four bits of
MISO have meaning; namely, they contain the content of the accessed register.
Figure 27. Data Format Description.
REGISTER DESCRIPTIONS
The following tables in this section describe the SPI register list and register bit meaning. Register reset values are also
described, along with the reset condition. A reset condition is the condition causing the bit to be set at the reset value.
Table 13. Possible Reset Conditions
Condition
Name
Definition
33742 Reset
POR
Power-ON Reset
33742 Mode
Transition
NR2R
Normal Request to Reset mode
NR2N
Normal Request to Normal mode
NR2STB
Normal Request to Standby mode
N2R
Normal to Reset mode
STB2R
Standby to Reset mode
STO2R
Stop to Reset mode
STO2NR
Stop to Normal Request
33742 Mode
RESET
33742S in Reset mode
Table 14. List of Registers
Register
Address
Formal Name
and Link
Comment and Use
Write
Read
MCR
$000
Selection for Normal, Standby, Sleep,
Stop, and Debug modes
BATFAIL, general failure, VDD pre-
warning, and Watchdog flag
RCR
$001
Configuration for reset voltage level, CAN Sleep and Stop modes
CAN
$010
CAN slew rate, Sleep and Wake-up
enable/disable modes, drive enable after
failure
CAN wake-up and CAN failure status bits
Bit 7
Bit 5
Bit 3
Bit 4
Bit 2
Bit 6
Bit 1 Bit 0
A2
A0
D3
R/W
D2
A1
D1
D0
MISO
MOSI
Address
Data
Note Read operation: R/W bit = logic [0]
Write operation: R/W = logic [1]
:
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