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參數(shù)資料
| 型號： | MC33298 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Eight Output Switch with Serial Peripheral Interface I/O(帶SPI接口的八輸出開關(guān)) |
| 中文描述： | 8個串行外圍接口的I / O（帶的SPI接口的八輸出開關(guān)輸出開關(guān)） |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 642K |
| 代理商： | MC33298 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33298
21
SFPD pin. When the SFPD pin is in a logic high state, an over
current condition will be reported on the SO pin. However,
limiting output current is in effect and the output is permitted to
operate if the over current condition does not drive output into
an over temperature fault. An over temperature fault will
shutdown the specific output effected for the duration of the
over temperature condition.
Over current and over temperature faults are often related.
Turning the effected output switches OFF and waiting for some
time to allow the output to cool down should make these types
of faults go away.
Soft
over current faults can sometimes be
determined over hard short faults and over temperature faults
by observing the time required for the device to recover.
However, in general over current and over temperature faults
can not be differentiated in normal application usage.
An advantage of the synchronous serial output is multiple
faults can be detected with only one (SO) pin being used for
fault status reporting.
If V
PWR
experiences an over voltage condition, all outputs
will immediately be turned OFF and remain latched off. A new
command word is required to turn the outputs back on following
an over voltage condition.
Output Voltage Clamping
Each output of the 33298 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of the
output. Each clamp independently limits the drain to source
voltage to 53 V at drain currents of 0.5 A and keeps the output
transistors from avalanching by causing the transient energy to
be dissipated in the linear mode. See Figure 19. The total
energy clamped (E
J
) can be calculated by multiplying the
current area under the current curve (I
A
) times the clamp
voltage (V
CL
) times the duration the clamp is active (t).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.5 A, indicate the maximum energy to
be 50 mJ at 150
°
C junction temperature per output.
Figure 19. Output Voltage Clamping
THERMAL CHARACTERIZATION
Thermal Model
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors of
power generation. The thermal model illustrated in Figure 20
was developed for the 33298 mounted on a typical PC board.
The model is accurate for both steady state and transient
thermal conditions. The components R
D0
through R
D7
represent
the steady state thermal resistance of the silicon die for
transistor outputs 0 through 7, while C
D0
through C
D7
represent
the corresponding thermal capacitance of the silicone die
translator outputs and plastic. The device area and die
thickness determine the values of these specific components.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by the
terms R
pkg
and C
pkg
. The steady state thermal resistance of
leads and the PC board make up the steady state package
thermal resistance, R
pkg
. The thermal capacitance of the
package is made up of the combined capacitance of the flag
and the PC board. The mode compound was not modeled as a
specific component but it is factored into the other overall
component values.
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected
to.The I
PWR
current source represents the total power
dissipation and is calculated by totalling the power dissipation
of each individual output transistor. This is easily accomplished
by knowing R
DS(on)
and load current of the individual outputs.
Very satisfactory steady state and transient results are
experienced with this thermal model. Tests indicate the model
accuracy to have less than 10 percent error. Output interaction
with an adjacent output is believed to be the main contributor to
the thermal inaccuracy. Tests indicate little or no detectable
thermal affects caused by distant output transistors isolated by
one or more other outputs. Tests were conducted with the
device mounted on a typical PC board placed horizontally in a
33 cubic inch still air enclosure. The PC board was made of FR4
material measuring 2.5 by 2.5 inches, having double sided
circuit traces of 1.0 ounce copper soldered to each device pin.
The board temperature was measured with thermal couple
soldered to the board surface one inch away from the center of
the device. The ambient temperature of the enclosure was
measured with a second thermal couple located over the center
of one inch distance from device.
Thermal Performance
Figure 20 illustrates the worst case thermal component
parameters values for the 33298 in the 20-pin plastic power DIP
and the SOP-24 wide body surface mount package. Pins 5, 6,
Current
Area (I
A
)
V
PWR
Time
GND
Drain-to-Source ON
Voltage (V
DS(on)
)
Drain Current
(I
D
= 0.5A)
Drain-to-Source Clamp
Voltage (V
CL
= 65 V)
Drain Voltage
Clamp Energy
(E
J
= I
A
x V
CL
x t)
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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