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參數(shù)資料
| 型號： | MC3110 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Pilot⑩ Motion Processor |
| 中文描述： | 試點⑩運動處理器 |
| 文件頁數(shù)： | 32/81頁 |
| 文件大小： | 1078K |
| 代理商： | MC3110 |
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MC3110 Technical Specifications
32
allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two
flops latch the incoming data in the interface latches by driving ~HG1, and ~HG2 low from the
start of the write transaction until the first negative clock transition after the first positive transition
following the start of the write cycle. This tail-biting circuit removes the requirement for hold time
on the data bus.
HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at
the top generates HCYC one clock interval after the interface has been accessed and the host has
finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is
preserved in the three flops F13, F8, and F9. A host write or a CP write, DSIW, enable REG1 and
REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates
~ENHD1 and ~ENHD2 for the data registers on the DATREG schematic. The logic at the bottom
of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the
CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST
INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all
host transactions except read status, and stays de-asserted until the CP has completed the DSIW
cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and
from the host use the data registers and do not interrupt the CP. The CP knows the number of data
transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least
significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the
schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves theses
bit set to 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched
read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until
after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS.
IOPIL16 4
The CP interface is shown in sheet IOPIL16 4. The incoming data DSD[15:0] is latched in the
transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from
the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL16 1 and
IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and
DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output
latches, which present the data during a CP read, are always transparent because GOUT is connected
to VDD. The latched I/O in the Actel part contains both input and output latches. The output
latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.
The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal
is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
IOPIL16 2
The CP control starts on IOPIL16 2. The I/O control is generated from ~CPSTRB, ~CPIS,
CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-
enable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold
times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be
used for this interface and the CP.
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