MC26LS30
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5
Table 1
Inputs
Outputs
Operation
VCC
VEE
Mode
A
B
C
D
A
B
C
D
Differential
+5.0
Gnd
0
1
0
Differential
(EIA422A)
+5.0
Gnd
0
1
0
1
0
1
0
1
0
1
(EIA 422 A)
0
1
X
0
1
0
1
Z
0
Z
0
1
0
X
1
0
1
0
Z
1
Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
1
0
Z
1
Z
SingleEnded
+5.0
5.0
1
0
S g e
ded
(EIA423A)
50
1
0
1
0
1
0
(EIA 423 A)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
X
Z
X = Don’t Care
Z = High Impedance (Off)
Figure 1. Differential Output Test
Figure 2. SingleEnded Output Test
VEE
Mode = 0
VOS
RL
RL/2
CL
Vin
(0.8 or 2.0 V)
VCC
VO
VCC
VOD2
Mode = 1
Vin
(0.8 or 2.0 V)
Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay
NOTES:
1. S.G. set to: f
p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns.
2. tSK1 = tPDHtPDL for each driver.
3. tSK2 computed by subtracting the shortest tPDH from the longest tPDH of the 2 drivers within a package.
4. tSK3 computed by subtracting the shortest tPDL from the longest tPDL of the 2 drivers within a package.
10%
tPDH
1.5 V
Vin
0 V
10%
50%
90%
tf
tPDL
tr
90%
50%
Vout
1.5 V
+3.0 V
VCC
Vin
S.G.
VOD
500 pF
100