參數(shù)資料
型號: MC14LC5482
廠商: Motorola, Inc.
元件分類: Codec
英文描述: PCM Codec-Filter(PCM 編解碼-濾波器)
中文描述: PCM編解碼器,過濾器(的PCM編解碼-濾波器)
文件頁數(shù): 6/16頁
文件大?。?/td> 313K
代理商: MC14LC5482
MC14LC5480EVK
6
MOTOROLA
SECTION 2 – HARDWARE DESCRIPTION
NOTE
Please refer to the MC14LC5480EVK schematic for the following discussion of the
hardware.
For the MC14LC5480 PCM Codec–Filter, Jumper J4 must be open. For the
MC145481, MC145482, MC145483, and MC145484, Jumper J4 must be con-
nected.
2.1
CLOCK GENERATION CIRCUITRY
A 4.096 MHz crystal oscillator is used as the system clock for the MC14LC5480EVK. From
this 4.096 MHz crystal, frame sync (FSYNC), bit clock (BCLK), and 256 kHz are derived for
use by the PCM Codec–Filter.
FSYNC
Frame sync (FSYNC) is generated on–board, and is controlled through J20A for FSR (frame
sync receive), and J16 for FST (frame sync transmit). Populating these jumpers also routes
the FSYNC to the 2x20 connector (P13), Pin 40 (FSR), and Pin 1 (FST).
S1 allows the user to select the “width” of FSYNC. The FSYNC pulse width is set as a num-
ber of BCLKs. The following number of BCLKs for FSYNC can be set with S1.
1–2–3–4–8–12–13–16
The switch S1 configurations for these settings are presented below.
Figure 2–1. Switch S1 Settings for FSYNC Duration
When configuring the MC14LC5480EVK to connect to the MC145532 ADPCM Transcoder,
the various transcoding rates of the MC145532 can be exercised using the S1 switch posi-
tions as shown in Figure 2–2. Refer to the MC145532 data sheet for relevant timing dia-
grams.
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