- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371017 > MC145740F (MOTOROLA INC) Dual Tone Multiple Frequency Line Interface PDF資料下載
參數(shù)資料
| 型號： | MC145740F |
| 廠商： | MOTOROLA INC |
| 元件分類： | 信令電路 |
| 英文描述： | Dual Tone Multiple Frequency Line Interface |
| 中文描述： | TELECOM, DTMF SIGNALING CIRCUIT, PDSO20 |
| 封裝： | SOG-20 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MC145740F |
MC145740
MOTOROLA
7
PIN DESCRIPTIONS
TxA1
Non–Inverting Analog Output (Pin 1)
This pin is the line driver non–inverting output. A + 7 dBm
(typ) differential output voltage can be obtained by connect-
ing a 1.2 k
load resistor between TxA1 and TxA2. Note that
the DSI input, if used, must be controlled for the output level
not to exceed the above signal level.
TxA2
Inverting Analog Output (Pin 2)
This pin is the driver inverting output. Refer to TxA1.
RxA
DTMF Receive Input (Pin 3)
This pin is the DTMF signal input (AGC input).
AGCout
AGC Output (Pin 4)
This pin is the AGC amplifier output. The signal received
from the RxA pin appears at this pin through the AGC amplifi-
er so that any signal receivers can be connected on this pin
to decode the non–DTMF signals. The AGC amplifier gain is
software programmable as shown in Table 3.
Vref
Reference Analog Ground (Pin 5)
This pin provides the analog ground voltage, VCC/2, which
is internally regulated from VCC. This pin should be
decoupled to GND with 0.1
μ
F and 100
μ
F capacitors.
FTLC1, FTLC2
Band–Pass Filter Test (Pins 6, 7)
These pins are high impedance filter outputs. They may be
used for testing the DTMF receive high and low band–pass
filter characteristics, and are reserved for manufacturer’s use
only. In normal operation, each pin is decoupled to Vref with
0.1
μ
F capacitors.
X1
Crystal Oscillator Output (Pin 8)
A 3.579545 MHz
±
0.1% crystal oscillator is tied to this pin
with the other end connected to X2.
X2
Crystal Oscillator Input (Pin 9)
A 3.579545 MHz
±
0.1% crystal oscillator is tied to this pin
with the other end connected to X1. X2 may be driven
directly from an appropriate external clock source. In this
case, X1 should be held open.
GND
Ground (Pins 10, 18)
Ground pins are connected to the system ground.
VCC
Power Supply (Pins 11, 19)
The digital supply pins are connected to the positive power
supply (5 V).
DV
DTMF Data Valid (Pin 12)
This pin goes low when valid DTMF tones are detected.
The guard time of DTMF tone detection (ton) and release
(toff) is programmed by two bits of serial data (CD1, CD0) as
shown in Table 2. This feature improves the immunity to the
short noise and momentary dropouts. See Figure 2 for the
detailed timing diagram.
TD
Tone Detect (Pin 13)
This pin goes low immediately after valid DTMF tones are
detected, regardless of the guard time set by two bits of
serial data. This pin also outputs the short high pulse when
the device detects the change of DTMF tones without a silent
period. For a detailed description, see Figure 2.
R/W
Read/Write Data Switch (Pin 14)
This pin is used for controlling the input/output direction of
the DATA I/O pin.
DATA
Serial Data Input/Output (Pin 15)
When the R/W pin is at logic low, the DATA pin works as
the 14–bit control register input which determines the func-
tion mode, DTMF tones, transmit level (or receiver gain lev-
el), detect time, and transmit squelch. When the R/W pin is at
logic high, the DATA pin works as the 4–bit status register
output which provides the hexadecimal codes corresponding
to the detected digit.
EN
Enable Input (Pin 16)
When the R/W pin is held low, high level input to this pin
transfers the 14 bits of control register data to the mode
control logic, then the function mode is immediately
changed. When this pin is at logic low, the control register
and the mode control logic are isolated. Therefore, the
14 bits of data in the control register must not be changed
while EN is at logic high level.
When the R/W pin is held high, the rising edge of the EN
pin loads the DTMF data from the DTMF decoder into the
status register, and shifts out the first bit (LSB = D0) to the
DATA pin.
CLK
SPI Clock Input (Pin 17)
This pin is the SPI clock input for the 14–bit control register
and the 4–bit status register. At the rising edge of CLK, the
14 bits of data are captured into the control register when
R/W is at logic low, and the 4 bits of data are shifted out from
the status register when R/W is at logic high.
DSI
Driver Summing Input (Pin 20)
This pin is the inverting input of the line driver. An external
signal source may be connected to this pin through a series
resistor RDSI, transmitting the signal from the TxA1 and
TxA2. The differential gain GDSI = (VTxA1 – VTxA2)/VDSI
is determined by the following equation:
GDSI = – 2 RF/RDSI, RF – 20 k
Note that the programmable transmit attenuator does not
affect this case.
The DSI pin should be held open when not in use.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145745FW | V.21/V.23 Telemeter Modem |
| MC145745 | V.21/V.23 Telemeter Modem |
| MC14576AF | Dual Video Amplifiers |
| MC14577CP | Triple Processor Supervisors 20-LCCC -55 to 125 |
| MC14576AP | Dual Video Amplifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC14574D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14575CL | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC14575CP | 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述: |
| MC14576CFEL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14577CF | 制造商:Freescale Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。