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參數(shù)資料
| 型號(hào)： | MC145707P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C |
| 中文描述： | LINE TRANSCEIVER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 229K |
| 代理商： | MC145707P |
MC145705
MC145706
MC145707
6
MOTOROLA
PIN DESCRIPTIONS
VCC
Digital Power Supply
This digital supply pin is connected to the logic power sup-
ply. This pin should have a 0.33
μ
F capacitor to ground.
GND
Ground
Ground return pin is typically connected to the signal
ground pin of the EIA–232–D connector (Pin 7) as well as to
the logic power supply ground.
VDD
Positive Power Supply
This is the positive output of the on–chip voltage doubler
and the positive power supply input of the driver/receiver
sections of the device. This pin requires an external storage
capacitor to filter the 50% duty cycle voltage generated by
the charge pump.
VSS
Negative Power Supply
This is the negative output of the on–chip voltage doubler/
inverter and the negative power supply input of the driver/
receiver sections of the device. This pin requires an external
storage capacitor to filter the 50% duty cycle voltage gener-
ated by the charge pump.
TxEN
Output Enable
This is the driver output enable pin. When this pin is in
logic low level, the condition of the driver outputs (Tx1 – Tx3)
are in keep OFF (mark
)
state.
STB
Standby
The device enters the standby mode while this pin is con-
nected to the logic high level. During the standby mode,
driver and receiver output pins become high impedance
state. In this condition, supply current ICC is below 10
μ
A
(Typ) and can be operated with low current consumption.
C2+, C2–, C1+, C1–
Voltage Doubler and Inverter
These are the connections to the internal voltage doubler
and inverter, which generate the VDD and VSS voltages.
Rx1, Rx2 (Rx3)
Receive Data Input
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space, and causes
the corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes
the DO pin to swing up to VCC.
DO1, DO2 (DO3)
Data Output
These are the receiver digital output pins, which swing
from VCC to GND. Each output pin is capable of driving one
LSTTL input load.
Output level of these pins is high impedance while in
standby mode.
DI1, DI2 (DI3)
Data Input
These are the high impedance digital input pins to the
drivers. Input voltage levels on these pins must be between
VCC and GND.
The level of these input pins are TTL/CMOS compatible.
Tx1, Tx2 (Tx3)
Transmit Data Output
These are the EIA–232–E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS.
The actual levels and slew rate achieved will depend on the
output loading (RL/CL).
The minimum output impedance is 300
when turned off.
SWITCHING CHARACTERISTICS
RECEIVER
DRIVER
50%
DI1 – DI3
(INPUT)
+ 3 V
0 V
tf
10%
90%
tr
tPHL
tPLH
VOL
VOH
Tx1 – Tx3
(OUTPUT
)
50%
Rx1 – Rx3
(INPUT)
+ 3 V
0 V
tf
10%
90%
tr
tPHL
tPLH
VOL
VOH
DO1 – DO3
(OUTPUT)
STB (INPUT)
Tx1 – Rx3
(OUTPUT)
RECEIVER
DRIVER
+ 5 V
0 V
VOL
VOH
+ 1.5 V
+ 1.5 V
+ 5 V
+ 5 V
– 5 V
– 5 V
tDAZ
tDZA
STB (INPUT)
DO1 – DO3
(OUTPUT)
+ 5 V
0 V
VOH
VOL
+ 1.5 V
+ 1.5 V
90%
90%
10%
10%
tRAZ
tRZA
HIGH Z
HIGH Z
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