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參數(shù)資料
| 型號(hào)： | MC145423DT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX UDLT/ISDN 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 收發(fā)器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
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MC145423
TELECOMMUNICATIONS
24
data buffer with data from the Rx pin on the next eight
falling edges of the TDC-RDC clock. The RE1 and
RE2 enables should be roughly leading edge aligned
with the TDC-RDC data clock. These enables are
rising edge sensitive and need not be high for the
entire B channel input period.
Slave Mode (CLKOUT UDLT-2): This pin
serves as a buffered output of the crystal frequency
divided by two.
RE2/BCLK
Receive Data Enable Input 2 or B Channel
Data Clock Output (Pin 23)
Master Mode (UDLT-1): This pin is high
impedance.
Master Mode (RE2 UDLT-2): See pin
description for RE1 (pin 22).
Slave Mode (BCLK UDLT-1 and UDLT-2):
This output provides the data clock for the telset
codec-filter. This clock signal is 128 kHz and begins
operating upon the successful demodulation of a burst
from the master. At this time, EN1-TE1 goes high and
BCLK starts toggling. BCLK remains active for
16 periods, at the end of which time it remains low
until another burst is received from the master. In this
manner, synchronization between the master and slave
is established and any clock slippage is absorbed each
frame. If TONE (pin 18) is brought high, then EN1-
TE1/RE1 are generated from an internal oscillator
until TONE is brought low, or an incoming burst from
the master is received. BCLK is disabled when LB is
held low.
Rx
Receive Data Input (Pin 24)
Master Mode (UDLT-1): The 8-bit B channel
data is clocked into the device on this pin, on the
falling edges of TDC-RDC, under the control of RE1.
Slave Mode (UDLT-1): The 8-bit B channel data
from the telset PCM codec-filter is input on this pin on
the eight falling edges of BCLK after RE1 goes high,
when EN2-TE2/SIE/B1B2, pin 16 is low. When EN2-
TE2/SIE/B1B2, pin16 is high, the receive data word is
latched in during the high period of EN1-TE1, pin 17
which is simultaneous with the transfer of the transmit
word. See the pin descriptions for EN2-TE2/SIE/
B1B2 and EN1-TE2 for more information.
Master Mode (UDLT-2): B channel data is input
on this pin and controlled by the RE1, RE2, and TDC-
RDC pins.
Slave Mode (UDLT-2): This pin is an input for
the B channel data. B channel 1 data is clocked in on
the first eight falling edges of the BCLK output
following the rising edge of the EN1 output. B channel
2 data is clocked in on the next eight falling edges of
the BCLK following the rising edge of the EN2
output.
LO2
Line Drive Output (Pin 25)
The LO2 pin, along with LO1 (pin 26) form a push-
pull output, to drive the twisted pair transmission line.
The UDLT-1 drives the twisted pair with a 10-bit,
256 kHz modified DPSK (MDPSK) burst, or a square
wave (set by pin 14 MOD TRI/SQ) burst, each 125
s.
The UDLT-2 drives the twisted pair with a 20-bit
512 kHz modulated burst. When these pins are idle
and set for square wave modulation, they rest at the
positive power supply voltage. When these pins are
idle and set for MDPSK, they rest at Vref. For power
supply voltages less than 4.5 V, squarewave
modulation must be used.
LO1
Line Driver Output (Pin 26)
See the pin description for LO2 (pin 25).
MASTER/SLAVE
Master/Slave Mode (Pin 27)
A logic low (0 V) on this pin selects master and a
logic high (VDD) selects slave.
VDD
Positive Supply (Pin 28)
This is the most positive power supply pin.
Acceptable operating voltages are from 4.5 V to 5.5 V.
TELECOMMUNICATIONS
21
MC145423
FRAME 10/20
(Pin 8)
The UDLT series of transceivers are designed to
operate using a ping-pong transmission scheme with
an 8 kHz burst rate. Each frame the master device
“pings” a burst of data to the slave, which responds
with a “pong” burst of data. This pin selects whether
this 8 kHz frame will have a 10-bit data burst for
UDLT-1 compatibility or a 20-bit data burst for
UDLT-2 compatibility.
A logic low (0 V) selects the UDLT-1 (MC145422/
MC145426) mode. This sets the device to operate with
one 64 kbps voice/data channel and two 8 kbps
signaling channels. A logic high (VDD) on this pin
selects the UDLT-2 (MC145421/MC145425) mode.
This sets the device to operate with two 64 kbps
channels and two 16 kbps channels (2B+2D).
SDCLK
D Channel Signaling Data Clock Input (Pin 9)
Master Mode (UDLT-2): This is the transmit and
receive data clock input for both D channels. See
SDO1 and SDO2 pin descriptions for more
information.
Master Mode (UDLT-1): High impedance.
Slave Mode (UDLT-2): This is the transmit and
receive data clock output for both D channels. It starts
on demodulation of a burst from the master device.
This signal is rising-edge aligned with the EN1 and
BCLK signals. After the demodulation of a burst, the
SDCLK line completes two cycles and then remains
low until the next burst from the master is
demodulated. In this manner, synchronization with the
master is established and any clock slip between
master and slave is absorbed each frame.
Slave Mode (UDLT-1): This pin outputs 8 kHz
equivalent to TE1.
SDO1 and SDO2
D Channel Signaling Data Outputs 1 and 2
(Pins 10 and 11)
Master Mode (UDLT-2): These serial outputs
provide the 16 kbps D channel signaling information
from the incoming burst. Two data bits should be
clocked out of each of these two outputs between the
rising edges of the MSI frame reference clock. The
rising edge of MSI produces the first bit of each
D channel on its respective pin. Circuitry then
searches for a negative D channel clock edge. This
tells the D channel data shift register to produce the
second D channel bit on the next rising edge of the
SDCLK. Further rising edges of the SDCLK
recirculate the D channel output buffer information.
Master Mode (UDLT-1): These outputs are
received signaling bits from the slave UDLT and
change state on the rising edge of MSI, if PD is high;
or at the end of demodulation, if PD is low.
Slave Mode (UDLT-2): These two pins are the
outputs for the 16 kbps D channels. These pins are
updated on the rising edges of the slave SDCLK
output pin.
Slave Mode (UDLT-1): These outputs are
received signaling bits from the master UDLT and
change state on the rising edge of TE1.
SE/(Mu/A)
Signaling Enable Input or Tone Format Input
(Pin 12)
Master Mode (SE): A low on this pin causes the
state of LB, PD, SDI1, and SDI2 to be stored.
Additionally, output pins VD, SDO1, and SDO2 will
be high impedance. This allows the device to be
bussed with other UDLTs using a common control bus.
A high on this pin returns the device to normal
operation.
Slave Mode (Mu/A): This pin allows the user to
select the PCM code format for the pacifier tone. A
high on this pin selects Mu-Law. A low on this pin
selects A-Law. The state of this pin determines the
PCM code sequence for the 500 Hz square wave tone
generated when the TONE pin input is high.
PD
Power Down Low (Pin 13)
Master Mode: When this pin is held low, the
device powers down, except for the circuitry necessary
to demodulate an incoming burst and to output VD
and the B and D channel data bits. When this pin is
brought high, the device waits for three positive MSI
edges or until the end of an incoming transmission
from the slave and then begins transmitting every MSI
period to the slave UDLT on the next rising edge of
MSI.
Slave Mode: This is a bidirectional pin with a
weak output driver that can be externally overdriven.
When this pin is floating and a burst from the master is
demodulated, the weak output drivers will try to force
PD high. The drivers will try to force PD low, if
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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