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參數(shù)資料
| 型號： | MC14526BFG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER BINARY 6BIT 16SOEIAJ |
| 產(chǎn)品變化通告： | 1Q2012 Discontinuation 30/Mar/2012 |
| 標準包裝： | 50 |
| 系列： | 4000B |
| 邏輯類型： | 二進制計數(shù)器，十進制 |
| 方向： | 下 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 4 |
| 復位： | 異步 |
| 計數(shù)速率： | 6.6MHz |
| 觸發(fā)器類型： | 正，負 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 供應商設(shè)備封裝： | 16-SOEIAJ |
| 包裝： | 管件 |
MC14526B
http://onsemi.com
2
FUNCTION TABLE
Inputs
Output
Resulting
Function
Clock Reset Inhibit
Preset
Enable
Cascade
Feedback
“0”
X
H
X
L
H
X
L
H
L
H
Asynchronous reset*
Asynchronous reset
X
L
X
H
X
L
Asynchronous preset
L
H
L
X
L
Decrement inhibited
H
L
No change** (inactive edge)
Decrement**
X = Don’t Care
NOTES:
** Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
PIN DESCRIPTIONS
Preset Enable (Pin 3) — If Reset is low, a high level on the
Preset Enable input asynchronously loads the counter with
the programmed values on P0, P1, P2, and P3.
Inhibit (Pin 4) — A high level on the Inhibit input pre
vents the Clock from decrementing the counter. With Clock
(pin 6) held high, Inhibit may be used as a negative edge clock
input.
Clock (Pin 6) — The counter decrements by one for each
rising edge of Clock. See the Function Table for level
requirements on the other inputs.
Reset (Pin 10) — A high level on Reset asynchronously
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
high, causes the “0” output to go high.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
other than all zeroes, the “0” output is valid after the rising
edge of Preset Enable (when Cascade Feedback is high). See
the Function Table.
Cascade Feedback (Pin 13) — If the Cascade Feedback
input is high, a high level is generated at the “0” output when
the count is all zeroes. If Cascade Feedback is low, the “0”
output depends on the Preset Enable input level. See the
Function Table.
P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
data inputs. P0 is the LSB.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the
synchronous counter outputs. Q0 is the LSB.
VSS (Pin 8) — The most negative power supply potential.
This pin is usually ground.
VDD (Pin 16) — The most positive power supply potential.
VDD may range from 3.0 to 18 V with respect to VSS.
STATE DIAGRAM
MC14526B
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
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