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參數(shù)資料
| 型號： | MC14521BFG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIVIDER 24STAGE FREQ 16SOEIAJ |
| 產(chǎn)品變化通告： | 1Q2012 Discontinuation 30/Mar/2012 |
| 標準包裝： | 50 |
| 系列： | 4000B |
| 邏輯類型： | 除以 2 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 24 |
| 計數(shù)速率： | 12MHz |
| 觸發(fā)器類型： | 負邊沿 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOEIAJ |
| 包裝： | 管件 |
MC14521B
http://onsemi.com
6
Figure 5. RC Oscillator Stability
Figure 6. RC Oscillator Frequency as a
Function of RTC and C
-55
-25
0
25
50
75
100
125
8.0
4.0
0
-4.0
-8.0
-12
-16
FREQUENCY
DEVIA
TION
(%)
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY
TEST CIRCUIT
FIGURE 7
VDD = 15 V
10 V
5.0 V
RTC = 56 kW,
C = 1000 pF
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
{
f,OSCILLA
T
OR
FREQUENCY
(kHz)
100
50
20
10
5.0
1.0
2.0
0.1
0.2
0.5
1.0 k
10 k
100 k
1.0 m
0.0001
0.001
0.01
0.1
RTC, RESISTANCE (OHMS)
C, CAPACITANCE (
mF)
VDD = 10 V
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
TEST CIRCUIT
FIGURE 7
f AS A FUNCTION
OF C
(RTC = 56 kW)
(RS = 120 k)
Figure 7. RC Oscillator Circuit
Figure 8. Functional Test Circuit
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
IN 1
IN 2
R
VDD
VDD′
VSS
VSS′
VDD
RS
RTC
C
Q18
Q19
Q20
Q21
Q22
Q23
Q24
OUT 1
OUT 2
IN 1
IN 2
R
VDD′
VDD
VSS
PULSE
GENERATOR
FUNCTIONAL TEST SEQUENCE
A test function (see Figure 8) has been included
for the reduction of test time required to exercise all
24 counter stages. This test function divides the
counter into three 8stage sections, and 255
counts are loaded in each of the 8stage sections
in parallel. All flipflops are now at a logic “1”. The
counter is now returned to the normal 24stages in
series configuration. One more pulse is entered into
Input 2 (In 2) which will cause the counter to ripple
from an all “1” state to an all “0” state.
Inputs
Outputs
Comments
Reset In 2
Out 2
VSS′ VDD′
Q18
thru
Q24
Counter is in three 8stage sections
in parallel mode Counter is reset. In 2
and Out 2 are connected together.
1
0
VDD
GND
VDD
0
1
First “0” to “1” transition on In 2,
Out 2 node.
0
1
0
1
255 “0” to “1” transitions are clocked
into this In 2, Out 2 node.
1
The 255th “0” to “1” transition.
0
1
0
1
Counter converted back to 24stages
in series mode.
1
0
1
Out 2 converts back to an output.
0
1
0
Counter ripples from an all “1” state
to an all “0” stage.
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