15
IC
CP Chip Pinouts
CP
Pin Name
Pin #
Description/Functionality
PWMMag1
PWMMag2
PWMMag3
PWMMag4
PWMMag5
PWMMag6
8
7
2
1
66
65
PWMmotor output magnitude signals (output). When the chip set is in PWMoutput mode
these pins provide the Pulse Width Modulated magnitude signal to the motor amplifier.The
PWMsignals are output for each motor axis as follows:
3-Phase Brushless
Signal Axis # Phase
PWMMag1
1
PWMMag2
1
PWMMag3
1
PWMMag4
2
PWMMag5
2
PWMMag6
2
2-Phase Brushless
Signal Axis # Phase
PWMMag1
1
PWMMag2
1
PWMMag3
2
PWMMag4
2
A
B
C
A
B
C
A
B
A
B
NOTE: If using the MC1231A with one axis in 3-phase and the other axis in 2-phase mode, to
avoid pin conflict, axis 1 should be assigned to 2-phase output, and axis 2 to 3-phase
The PWMresolution is 10 bits, frequency = 24.5Kz.
Positive limt switch input for axis 1-2. These signals provide directional limt inputs for the
positive-side travel limt of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. (See Host Command Section for more info.) If not used these signals should be
tied low for the default interpretation, or tied high if the interpretation is reversed.
CP
PosLimt1
PosLimt2
52
45
NOTE: For MC1231A both pins are valid. For MC1131A pins for axes 1 only are valid. Invalid
axis pins can be left un connected.
Negative limt switch input for axis 1-2. These signals provide directional limt inputs for the
negative-side travel limt of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. (See Host Command Section for more info.) If not used these signals should be
tied low for the default interpretation, or tied high if the interpretation is reversed.
CP
NegLimt1
NegLimt2
51
44
NOTE: For MC1231A both pins are valid. For MC1131A pins for axis 1 only are valid. Invalid
axis pins can be left un connected.
Axis Address used during 16-bit DAC motor command output (output). These signals encode
the motor output axis address as shown in the table below (both 3-phase and 2-phase
waveforms)
CP
DAC16Addr0
DAC16Addr1
30
29
Dac16Addr1 Dac16Addr0 Addressed Encoder
Low
Low
Low
High
High
Low
High
High
Axis 1 phase A
Axis 1 phase B
Axis 2 phase A
Axis 2 phase B
Note: When connecting to 3-phase brushless motors only two of the three required phase
outputs are provided in the DAC output mode. The third phase (phase C) is constructed
external to the chipset, usually by the amplifier. See theory of operations for more
information.
To write a valid DAC motor command value DACSlct (I/O chip) and I/OAddr0-3 (CP chip)
must be high, and I/OWrite (CP chip) must be low. The 16 bit DAC data word is organized as
follows: High twelve bits are in Data0-11 (CP chip), and low 4 bits are in DACLow0-3 (CP
chip).
Clock In (input). This pin provides the chip set master clock (Fclk = 25.0 Mhz)
CP
ClkIn
24