參數(shù)資料
型號(hào)： MC145192F
廠商： MOTOROLA INC
元件分類： XO, clock
英文描述： Low-Voltage 1.1 GHz PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20
封裝： SOG-20
文件頁(yè)數(shù)： 9/24頁(yè)
文件大小： 348K
代理商： MC145192F
MC145192
MOTOROLA
9
The fV signal appears as normally low and pulses high. The
fV signal can be used to verify the operation of the prescaler,
A counter, and N counter. The divide ratio between the fin
input and the fV signal is N
×
64 + A. N is the divide ratio of
the N counter and A is the divide ratio of the A counter. These
ratios are determined by bits loaded into the A register. See
Figure 16. The maximum frequency at which the phase de-
tectors operate is 1 MHz. Therefore, the frequency of fV
should not exceed 1 MHz.
If A23 = low and A22 = high, Output A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the Clock input. Upon power up, Output A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, Output A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit is
high.
Output B (Pin 15)
Open–Drain Digital Output. This signal is a general–pur-
pose digital output which may be used as an MCU port ex-
pander. This signal is low when the Out B bit (C0) of the
C register is low. When the Out B bit is high, Output B as-
sumes the high–impedance state. Output B may be pulled up
through an external resistor or active circuitry to any voltage
less than or equal to the potential of the VPD pin. Note: the
maximum voltage allowed on the VPD pin is 5.5 V for the
MC145192.
Upon power–up, power–on reset circuitry forces Output B
to a low level.
REFERENCE PINS
REFin and REFout (Pins 20 and 1)
Configurable Pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 17.
In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–reso-
nant crystal. Frequency–setting capacitors of appropriate
values as recommended by the crystal supplier are con-
nected from each of the two pins to ground (up to a maximum
of 30 pF each, including stray capacitance). An external re-
sistor of 1 M
to 15 M
is connected directly across the pins
to ensure linear operation of the amplifier. The device is de-
signed to operate with crystals up to 10 MHz; the required
connections are shown in Figure 9. To turn on the oscillator,
bits R15, R14, and R13 must have an octal value of one (001
in binary). This is the active–crystal mode shown in
Figure 17. In this mode, the crystal oscillator runs and the
R Counter divides the crystal frequency, unless the part is in
standby. If the part is placed in standby via the C register, the
oscillator runs, but the R counter is stopped. However, if bits
R15 to R13 have a value of 0, the oscillator is stopped, which
saves additional power. This is the shut–down crystal mode
shown in Figure 17, and can be engaged whether in standby
or not.
In the reference mode, REFin (Pin 20) accepts a signal up
to 20 MHz from an external reference oscillator, such as a
TCXO. A signal swinging from at least the VIL to VIH levels
listed in the Electrical Characteristics table may be directly
coupled to the pin. If the signal is less than this level, ac cou-
pling must be used as shown in Figure 8. The ac–coupled
signal must be at least 400 mV p–p. Due to an on–board re-
sistor which is engaged in the reference modes, an external
biasing resistor tied between REFin and REFout is not
required.
With the reference mode, the REFout pin is configured as
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REFout is
the REFin frequency divided by 16. In addition, Figure 17
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REFout pin is
5 MHz for VDD to VSS swing. Therefore, for REFin frequen-
cies above 5 MHz, the one–to–one ratio may not be used for
large signal swing requirements. Likewise, for REFin fre-
quencies above 10 MHz, the ratio must be more than two.
If REFout is unused, an octal value of two should be used
for R15, R14, and R13 and the REFout pin should be floated.
A value of two allows REFin to be functional while disabling
REFout, which minimizes dynamic power consumption and
electromagnetic interference (EMI).
LOOP PINS
fin and fin (Pins 11 and 10)
Frequency Input from the VCO. These pins feed the on–
board RF amplifier which drives the 64/65 prescaler. These
inputs may be fed differentially. However, they are usually
used in a single–ended configuration as shown in Figure 7.
Note that fin is driven while fin must be tied to ground via a
capacitor.
Motorola does not recommend driving fin while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
PDout (Pin 6)
Single–Ended Phase/Frequency Detector Output. This is
a 3–state current–source/sink output for use as a loop error
signal when combined with an external low–pass filter. The
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detector is
described below and is shown in Figure 19.
POL bit (C7) in the C register = low (see Figure 15)
Frequency of fV > fR or Phase of fV Leading fR: current–
sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
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