參數(shù)資料
型號(hào)： MC145192
廠商： Motorola, Inc.
英文描述： Low-Voltage 1.1 GHz PLL Frequency Synthesizer
中文描述： 低電壓1.1 GHz PLL頻率合成器
文件頁(yè)數(shù)： 4/24頁(yè)
文件大?。?/td> 348K
代理商： MC145192
MC145192
4
MOTOROLA
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PDout
(Iout
≤
2 mA, VDD = VCC = 2.7 to 5.0 V, Voltages Referenced to GND, VDD = VCC
≤
VPD)
Parameter
Test Condition
VPD
4.5
Guaranteed
Limit
Unit
Maximum Source Current Variation Part–to–Part
Vout = 0.5 x VPD
±
20
%
5.5
±
20
Maximum Sink–versus–Source Mismatch
Vout = 0.5 x VPD
4.5
12
%
(Note 3)
5.5
12
Output Voltage Range
Iout variation
≤
20%
4.5
0.5 to 4.0
V
(Note 3)
5.5
0.5 to 5.0
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within – 40
°
to 85
°
C.
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.0 V, TA = – 40
°
to 85
°
C, CL = 50 pF, Input tr = tf = 10 ns, VPD = 2.7 to 5.5 V with VDD
≤
VPD)
Symbol
Parameter
Guaranteed
Limit
Unit
fclk
Serial Data Clock Frequency (Figure 1)
NOTE: Refer to Clock tw below
dc to 2.0
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Output A (Selected as Data Out) (Figures 1 and 5)
200
ns
tPLH,
tPHL
Maximum Propagation Delay, Enable to Output A (Selected as Port) (Figures 2 and 5)
200
ns
tPZL,
tPLZ
Maximum Propagation Delay, Enable to Output B (Figures 2 and 6)
200
ns
tTLH,
tTHL
Maximum Output Transition Time, Output A and Output B; tTHLonly, on Output B
(Figures 1, 5, and 6)
200
ns
Cin
Maximum Input Capacitance — Data In, Clock, Enable
10
pF
TIMING REQUIREMENTS
(VDD = VCC = 2.7 to 5.0 V, TA = – 40
°
to 85
°
C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
Guaranteed
Limit
Unit
tsu, th
tsu, th,
trec
Minimum Setup and Hold Times, Data In versus Clock (Figure 3)
50
ns
Minimum Setup, Hold and Recovery Times, Enable versus Clock (Figure 4)
100
ns
tw
tw
tr, tf
Minimum Pulse Width, Enable (Figure 4)
*
cycles
Minimum Pulse Width, Clock (Figure 1)
250
ns
Maximum Input Rise and Fall Times, Clock (Figure 1)
100
μ
s
* The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
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