參數(shù)資料
型號: MC14517B
廠商: ON SEMICONDUCTOR
英文描述: Dual 64 Bit Static Shift Register(雙64位移位寄存器)
中文描述: 雙64位靜態(tài)移位寄存器(雙64位移位寄存器)
文件頁數(shù): 2/7頁
文件大?。?/td> 158K
代理商: MC14517B
MC14517B
http://onsemi.com
2
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
T
A
Operating Temperature Range
55 to +125
°
C
T
stg
Storage Temperature Range
65 to +150
°
C
T
L
Lead Temperature
(8
Second Soldering)
260
°
C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high
impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
C
B
WE
B
Q48
B
Q16
B
V
DD
D
B
Q32
B
Q64
B
C
A
WE
A
Q48
A
Q16
A
V
SS
Q32
A
Q64
A
D
A
FUNCTIONAL TRUTH TABLE
(X = Don’t Care)
Clock
0
Write
Enable
0
Data
X
16
Bit Tap
Content of 16
Bit
Displayed
High Impedance
Content of 16
Bit
Displayed
High Impedance
Content of 16
Bit
Displayed
Data at tap
entered into 17
Bit
Content of 16
Bit
Displayed
High Impedance
32
Bit Tap
Content of 32
Bit
Displayed
High Impedance
Content of 32
Bit
Displayed
High Impedance
Content of 32
Bit
Displayed
Data at tap
entered into 33
Bit
Content of 32
Bit
Displayed
High Impedance
48
Bit Tap
Content of 48
Bit
Displayed
High Impedance
Content of 48
Bit
Displayed
High Impedance
Content of 48
Bit
Displayed
Data at tap
entered into 49
Bit
Content of 48
Bit
Displayed
High Impedance
64
Bit Tap
Content of 64
Bit
Displayed
High Impedance
Content of 64
Bit
Displayed
High Impedance
Content of 64
Bit
Displayed
High Impedance
0
1
1
0
X
X
1
1
0
X
Data entered
into 1st Bit
Data entered
into 1st Bit
X
1
0
Content of 64
Bit
Displayed
High Impedance
1
X
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