參數(shù)資料
型號: MC14516BD
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Binary Up/Down Counter
中文描述: 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16
封裝: PLASTIC, SOIC-16
文件頁數(shù): 1/10頁
文件大?。?/td> 258K
代理商: MC14516BD
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
393
MC14516B
The MC14516B synchronous up/down binary counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure.
This counter can be preset by applying the desired value, in binary, to the
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the
reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
Single Pin Reset
Asynchronous Preset Enable Operation
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
V
Input or Output Current (DC or Transient),
per Pin
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
TRUTH TABLE
Carry In
1
0
0
X
X
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
Up/Down
X
1
0
X
X
Preset
Enable
Reset
0
0
0
0
1
Clock
X
Action
No Count
Count Up
Count Down
Preset
Reset
0
0
0
1
X
X
X
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55
°
to 125
°
C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
VDD = PIN 16
VSS = PIN 8
6
11
14
2
7
Q0
Q1
Q2
Q3
CARRY
OUT
PE
CARRY IN
RESET
UP/DOWN
CLOCK
P0
P1
P2
P3
1
5
9
10
15
4
12
13
3
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