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參數(shù)資料
| 型號(hào)： | MC145166 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLLs for 46/49 MHz Cordless Telephones |
| 中文描述： | 為46/49兆赫無繩電話雙PLL |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 135K |
| 代理商： | MC145166 |
MC145166
MC145167
MOTOROLA
7
Table 1. MC145166/67 Divide Ratios and VCO Frequencies
Handset (Mode = 0)
Base (Mode = 1)
Channels
Transmit
Receive
Transmit
Receive
D3
D2
D1
D0
CH#
fin2 (MHz)
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
N
fin1 (MHz)
35.915
35.935
35.975
36.015
36.035
36.075
36.135
36.175
36.235
36.275
N
fin2 (MHz)
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
N
fin1 (MHz)
38.975
39.150
39.165
39.075
39.180
39.135
39.195
39.235
39.295
39.275
N
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
9934
9969
9972
9954
9975
9966
9978
9986
9998
9994
7183
7187
7195
7203
7207
7215
7227
7235
7247
7255
9322
9326
9334
9342
9346
9354
9366
9374
9386
9394
7795
7830
7833
7815
7836
7827
7839
7847
7859
7855
NOTES:
1. Other input combinations will be defaulted to channel 10.
2. 0 = logic low, 1 = logic high.
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| MC145166DW | 制造商:Motorola Inc 功能描述:PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
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