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參數(shù)資料
| 型號： | MC145166 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLLs for 46/49 MHz Cordless Telephones |
| 中文描述： | 為46/49兆赫無繩電話雙PLL |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MC145166 |
MC145166
MC145167
6
MOTOROLA
PIN DESCRIPTIONS
INPUT PINS
OSCin/OSCout
Reference Oscillator Input/Output (Pins 1,16)
These pins form a reference oscillator when connected to
an external parallel–resonant crystal. For a 46/49 MHz cord-
less phone application, a 10.24 MHz crystal is needed.
OSCin may also serve as input for an externally generated
reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required for OSCout.
MODE
Mode Select (Pin 2)
Mode is for determining whether the part is to be used in
the base or handset of a cordless phone. Internally, this pin is
used in the decoding logic for selecting the ROM address.
When high, the device is set in the base mode, and when
low, it is set in the handset mode. This input has an internal
pull–down device.
SB
Standby Input (Pin 3)
The standby pin is used to save power when not transmit-
ting. When high, both the transmit and receive loops are in
operation. When low, the transmit loop is disabled, thereby
reducing power consumption. This input has an internal pull–
down device.
D0 – D3
Data Inputs (MC145166 — Pins 5 – 8)
These inputs provide the BCD code for selecting the one
of ten channels to be locked in both the transmit and receive
loop. When address data other than 1 – 10 are input, the de-
coding logic defaults to channel 10. The frequency assign-
ments with reference to Mode and D0 – D3 are shown in
Table 1. These inputs have internal pull–down devices.
fin1, fin2
Frequency Inputs (Pins 14, 9)
fin1 and fin2 are inputs to the divide–by–N receive and
transmit counters, respectively. These signals are typically
derived from the loop VCO and are ac coupled. For larger
amplitude signals (standard CMOS logic levels), dc coupling
may be used. The minimum input level is 200 mV p–p.
CLK, DATA
Clock, Data (MC145167 — Pins 5, 6)
These pins provide the BCD input by using serial channel
programming instead of parallel. Logical high represents a 1.
Each low–to–high transition of the clock shifts one bit of data
into the on–chip shift register.
ENB
Enable (MC145167 — Pin 8)
The enable pin controls the data transfer from the shift reg-
ister to the 4–bit latch. A positive pulse latches the data.
OUTPUT PINS
5 k
5 kHz Tone Signals (Pin 4)
The 5 kHz tone signals are N–channel, open–drain out-
puts derived from the reference oscillator.
LD
Lock Detect Signal (Pin 10)
The lock detect signal is associated with the transmit loop.
The lock output goes high to indicate an out–of–lock condi-
tion. This is a P–channel open–drain output.
PD1, PD2
Phase Detector Outputs (Pins 13, 11)
These are three–state outputs of the transmit and receive
phase detectors for use as loop error signals. Phase detector
gain is VDD/4
π
volts per radian.
Frequency fv > fr or fv leading: Output = Negative pulses
Frequency fv < fr or fv lagging: Output = Positive pulses
Frequency fv = fr and phase coincidence: Output = High–
impedance state
POWER SUPPLY
VSS
Negative Power Supply (Pin 12)
This pin is the negative supply potential and is usually
ground.
VDD
Positive Power Supply (Pin 15)
This pin is the positive supply potential and may range
from + 2.5 to + 5.5 V with respect to VSS.
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