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參數(shù)資料
| 型號： | MC145162D |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
| 封裝： | SOG-16 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MC145162D |
MC145162
MC145162–1
MOTOROLA
3
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Rating
Value
Unit
VDD
Vin
Iin, Iout
IDD, ISS
Tstg
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
DC Supply Voltage
– 0.5 to + 6.0
V
Input Voltage, All Inputs
– 0.5 to VDD + 0.5
10
V
DC Current Drain Per Pin
mA
DC Current Drain VDD or VSS Pins
Storage Temperature Range
30
mA
– 65 to + 150
°
C
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, TA = 25
°
C)
Symbol
b l
Characteristic
i i
VDD
Guaranteed Limit
U i
Unit
Min
Max
VDD
VOL
Power Supply Voltage Range
—
2.5
5.5
V
Output Voltage
(Iout= 0)
0 Level
2.5
5.5
—
—
0.1
0.1
V
VOH
(Vin= VDD or 0)
1 Level
2.5
5.5
2.45
5.45
—
—
VIL
Input Voltage
(Vout= 0.5 V or VDD– 0.5 V)
0 Level
2.5
5.5
—
—
0.75
1.65
V
VIH
1 Level
2.5
5.5
1.75
3.85
—
—
IOH
Output Current
(Vout= 2.2 V)
(Vout= 5.0 V)
Source
2.5
5.5
– 0.18
– 0.55
—
—
mA
IOL
(Vout= 0.3 V)
(Vout= 0.5 V)
Sink
2.5
5.5
0.18
0.55
—
—
IIL
Input Current
(Vin= 0)
OSCin, fin–T, fin–R
2.5
5.5
—
—
– 30
– 66
μ
A
ADin, CLK, Din, ENB
2.5
5.5
—
—
– 1.0
– 1.0
IIH
(Vin= VDD– 0.5)
OSCin, fin–T, fin–R
2.5
5.5
—
—
30
66
ADin, CLK, Din, ENB
2.5
5.5
—
—
5.0
5.0
IOZ
Cin
Cout
Three–State Leakage Current (Vout= 0 V or 5.5 V)
Input Capacitance
5.5
—
±
100
nA
—
—
8.0
pF
Output Capacitance
—
—
8.0
pF
IDD(stdby)
Standby Current
(All Counters are in Power–Down Mode with Oscillator On)
2.5
5.5
—
—
0.3
1.5
mA
IDD
Operating Current
MC145162: 200 mV p–p input at fin–T and fin–R = 60 MHz
MC145162–1: 250 mV p–p input at fin–T and fin–R = 85 MHz
with OSC = 10.24 MHz
2.5
5.5
—
—
3.0
10
mA
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid application of any voltage
higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and Vout should be constrained to the range
VSS
≤
(Vin or Vout)
≤
VDD.
Unused pins must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
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