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參數資料
| 型號： | MC145156P2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 22 MHz, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數： | 18/36頁 |
| 文件大小： | 718K |
| 代理商： | MC145156P2 |
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MC145151–2 through MC145158–2
18
MOTOROLA
14–BIT SHIFT REGISTER
14–BIT
÷
N COUNTER
φ
V
φ
R
MC145157–2 BLOCK DIAGRAM
REFERENCE COUNTER LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PDout
fin
OSCin
OSCout
ENB
14
14
14–BIT SHIFT REGISTER
DATA
CLK
14
REFout
÷
N COUNTER LATCH
14–BIT
÷
R COUNTER
14
S/Rout
fR
fV
1–BIT
CONTROL
S/R
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the
÷
N counter. This input has an
inverter biased in the linear region to allow use with ac
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), dc coupling may be
used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the clock shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷
N counter latch. The entry format is as follows:
L
M
C
FIRST DATA BIT INTO SHIFT REGISTER
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or
÷
N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the
÷
N latches are activated
if the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed
high to transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSCout to ground.
OSCin may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSCout.
OUTPUT PINS
PDout
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φ
R,
φ
V
Double–Ended Phase Detector B Outputs (Pins 16, 15)
These outputs can be combined externally for a loop–error
signal. A single–ended output is also available for this pur-
pose (see
PDout
).
相關PDF資料 |
PDF描述 |
|---|---|
| MC145151FN2 | Parallel-Input PLL Frequency Synthesizer |
| MC145152DW2 | Parallel-Input PLL Frequency Synthesizer |
| MC145155P2 | CONNECTOR ACCESSORY |
| MC145157P2 | Parallel-Input PLL Frequency Synthesizer |
| MC145157DW2 | Parallel-Input PLL Frequency Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC145159FN1R2 | 制造商:Motorola Inc 功能描述: |
| MC145159P1 | 制造商:Motorola Inc 功能描述: |
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