
MC145151-2 and MC145152-2 Technical Data, Rev. 5
20
Freescale Semiconductor
Design Considerations
For VDD = 5.0 V, the crystal should be specified for a loading capacitance, CL, which does not exceed
32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to 15 MHz, and
10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC
capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across the crystal can be estimated to be:
where
CO = the crystal's holder capacitance (see Figure 15) Figure 14. Parasitic Capacitances of the Amplifier
Figure 15. Equivalent Crystal Networks
The oscillator can be “trimmed” on-frequency by making a portion or all of C1 variable. The crystal and
associated components must be located as close as possible to the OSCin and OSCout pins to minimize
distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for Cin and Cout.
Power is dissipated in the effective series resistance of the crystal, Re, in Figure 15. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage
or excessive shift in frequency. R1 in
Figure 13 limits the drive level. The use of R1 may not be necessary
in some cases (i.e., R1 = 0
).
CL =
CinCout
Cin + Cout
+ Ca + Co +
C1C2
C1+C2
Cin
Cout
Ca
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
2
1
2
1
2
1
RS
LS
CS
Re
Xe
CO