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參數(shù)資料
| 型號： | MC145151FN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 6 MHz, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 718K |
| 代理商： | MC145151FN2 |
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MC145151–2 through MC145158–2
MOTOROLA
11
OUTPUT PINS
PDout
Phase Detector A Output (PDIP, SOG – Pin 6)
Three–state output of phase detector for use as loop error
signal. Double–ended outputs are also available for this pur-
pose (see
φ
V and
φ
R).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φ
R,
φ
V
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also avail-
able for this purpose (see
PDout
).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by
φ
V pulsing low.
φ
R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by
φ
R pulsing low.
φ
V remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φ
V and
φ
R remain high except for a small minimum time
period when both pulse low in phase.
LD
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). LD pulses low when loop is out of
lock.
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14;
SOG – Pins 14, 15)
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
15 V, independent of the VDD supply voltage. These are
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
REFout
Buffered Reference Oscillator Output (PDIP, SOG –
Pin 15)
Buffered output of on–chip reference oscillator or exter-
nally provided reference–input signal.
POWER SUPPLY
VDD
Positive Power Supply (PDIP, SOG – Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (PDIP, SOG – Pin 7)
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
fin
3
LED DISPLAY
MC14489
KEYBOARD
CMOS
MPU/MCU
ENB
CLK
DATA
1/2 MC1458*
MC145155–2
MC12073/74
PRESCALER
UHF/VHF
TUNER OR
CATV
FRONT END
4.0 MHz
φ
V
φ
R
+
–
* The
φ
R and
φ
V outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
for additional information. The
φ
R and
φ
V outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145152DW2 | Parallel-Input PLL Frequency Synthesizer |
| MC145155P2 | CONNECTOR ACCESSORY |
| MC145157P2 | Parallel-Input PLL Frequency Synthesizer |
| MC145157DW2 | Parallel-Input PLL Frequency Synthesizer |
| MC145167DW | Dual PLLs for 46/49 MHz Cordless Telephones |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145151P2 | 制造商:Motorola Inc 功能描述:Frequency Synthesizer, 28 Pin, Plastic, DIP |
| MC145152DW2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145152DW2R2 | 功能描述:IC PAR-IN PLL FREQ SYNTH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145155P | 制造商:Motorola Inc 功能描述: |
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
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