- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371013 > MC145074D (MOTOROLA INC) Simple -48V Hot Swap Controller with Enable 8-MSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號： | MC145074D |
| 廠商： | MOTOROLA INC |
| 元件分類： | DAC |
| 英文描述： | Simple -48V Hot Swap Controller with Enable 8-MSOP -40 to 85 |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 179K |
| 代理商： | MC145074D |
MC145074
7
MOTOROLA
$80000
$7FFFF
1
20–BIT DIGITAL INPUT
SCALER
OUTPUT
SCALER TRANSFER FUNCTION
3/4 SCALE = – 2.5 dB
1 – IDEAL
2 – ACTUAL
3 – COMPENSATED
3
2
Figure 10. Offset Scaler Operation
SERIAL INTERFACE AND CONTROL LOGIC
The serial interface and control logic of the MC145074
may be configured to accept 16, 18, or 20–bit data words by
applying the appropriate logic levels to the RES1 and RES0
pins. The DMODE input pin configures the serial interface to
accept 2’s complement data (MSB first) in a dual data pin or
single pin, multiplexed input format. It should be noted that in
some cases when using the single data pin input mode and a
large OSR, the BCLK rate may be too high for some DSPs,
unless an interface circuit is added. Figure 9 shows the avail-
able serial interface formats of the MC145074.
When operating in a dual data pin mode, 2’s complement
data words are serially input from the DIR and DIL pins as
shown in Figure 12. A rising edge on BCLK serially shifts in
the data present on the DIR and DIL inputs. After all data bits
of an input word are shifted in, a falling edge on WCLK
latches the data word into the MC145074. The BCLK can be
a continuous clock as long as the serial input data word is
right justified in the word time, or as long as there exists one
and only one BCLK cycle for every data bit input to the
device.
When operating in a single pin multiplexed mode, the DIR
input pin is reconfigured as the DILR pin. Left and right chan-
nel serial input data is multiplexed into the MC145074 on the
DILR pin, and is serially shifted into the part using BCLK as
shown in Figure 13. When WDLY is low, left channel data is
latched into the part on the rising edge of WCLK, and right
channel data is latched on the falling edge of WCLK. As in
the dual data pin mode, the BCLK can be either an asynchro-
nous or continuous clock as long as the serial input data
word is right justified in the word time. Forcing WDLY high al-
lows the WCLK cycle to appear one clock cycle early as
shown in Figure 14.
相關PDF資料 |
PDF描述 |
|---|---|
| MC145076D | MC145076 Stereo Audio FIR Smoothing Filter |
| MC145100AL | 4 X 4 CROSSPOINT SWITCH WITH CONTROL MEMORY |
| MC142100 | 10 AMP SUBMINIATURE POWER RELAY |
| MC142100AL | Floating-Point Digital Signal Processors, Military 325-CPGA -55 to 125 |
| MC142100AP | 4 X 4 CROSSPOINT SWITCH WITH CONTROL MEMORY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC14508BBJBS | 制造商:Motorola Inc 功能描述: |
| MC145100CP | 制造商:Motorola Inc 功能描述: |
| MC145106DW | 制造商:Motorola Inc 功能描述: |
| MC14510B | 制造商:Motorola Inc 功能描述: |
| MC14510BCP | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。