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參數(shù)資料
| 型號： | MC145074D |
| 廠商： | MOTOROLA INC |
| 元件分類： | DAC |
| 英文描述： | Simple -48V Hot Swap Controller with Enable 8-MSOP -40 to 85 |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 179K |
| 代理商： | MC145074D |
MC145074
3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table at 50 pf Loads on Outputs)
Symbol
Parameter
Figure
Guaranteed
Limit
Unit
Operating Frequency Xin
(DIV2 = 0)
(DIV2 = 1)
18.5
37.0
MHz
Bit Clock Frequency
18.5
MHz
tr, tf
tPLH
tTLH
Maximum Rise and Fall Times (BCKL, WCLK)
2, 5
6
ns
Xout L–H Propagation Delay
Xout Rise Time
2
30
15
ns
tPHL
tTHL
Xout H–L Propagation Delay
Xout Fall Time
2
30
15
ns
tPLH
tTLH
DOL, DOR L–H Propagation Delays
DOL, DOR Rise Time
3
15
5
ns
tPHL
tTHL
DOL, DOR H–L Propagation Delays
DOL, DOR Fall Time
3
15
5
ns
tPLH
tTLH
WCLK Output L–H Propagation Delay
WCLK Output Rise Time
4
15
5
ns
tPHL
tTHL
WCLK Output H–L Propagation Delay
WCLK Output Fall Time
4
15
5
ns
tsu
th
DIR Master Program Mode Minimum Setup Time
DIR Master Program Mode Minimum Hold Time
5
5
5
ns
tsu
th
DIR, DIL Minimum Setup Time
DIR, DIL Minimum Hold Time
5
5
5
ns
tsu
th
WCLK Minimum Setup Time to BCLK (not DMODE = WDLY = 1)
WCLK Minimum Hold Time to BCLK (not DMODE = WDLY = 1)
6
5
5
ns
tsu
th
WCLK Minimum Setup Time to Xin (not DMODE = WDLY = 1)
WCLK Minimum Hold Time to Xin (not DMODE = WDLY = 1)
6
5
5
ns
tsu
th
WCLK Minimum Setup Time to BCLK (DMODE = WDLY = 1)
WCLK Minimum Hold Time to BCLK (DMODE = WDLY = 1)
7
5
5
ns
tLAG
tLEAD
BCLK to Xin (1st Edge Only) Lag Time (DMODE = WDLY = 1)
BCLK to Xin (1st Edge Only) Lead Time (DMODE = WDLY = 1)
7
5
5
ns
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