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參數(shù)資料
| 型號： | MC145073DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | Dual 16-Bit Stereo Audio Sigma-Delta ADC |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MC145073DW |
MOTOROLA
MC145073
7
AC ELECTRICAL SPECIFICATIONS
(Full temperature and voltage ranges per Operation Ranges table. All timing parameters measured with respect to 30% and 70% of VDD(D)
unless otherwise noted.)
Figure
Symbol
Parameter
Divide
Ratio
Min
Max
Unit
6
1/tclk
1/tclki
Master Clock (CLK) Frequency (Note 1)
3.072
18.432
MHz
6
Internal Clock Frequency, CLKI (Note 1)
tclki = 1/(fclk/Divide Ratio)
3.072
6.144
MHz
6
twch
Master Clock High, CLK
1
2, 3
38
20
ns
6
twcl
Master Clock Low, CLK
1
2, 3
38
20
ns
7
tsync
twsh
Cin
Sync Period (Master and Slave Modes)
128 * tclki
20
128 * tclki
126 * tclki
20
ns
7
Sync High (Slave Mode)
ns
Input Capacitance
(Except for Left/Right Channel Inputs)
pF
Master Mode: ISLAV = 0
SCLK Period
8
tsclk
twl/twh
tCSY
2 * tclki
0.667
2 * tclki
1.50
ns
8
SCLK Duty Cycle
8
Propagation Delay (Note 2)
CLK Falling Edge to SYNC
CLK Rising Edge to SYNC
CLK Falling Edge to SYNC
1
2
3
40
tclk + 40
2 * tclk + 40
ns
ns
ns
8
tCSC
Propagation Delay (Note 2)
CLK Falling Edge to SCLK
CLK Rising Edge to SCLK
CLK Falling Edge to SCLK
1
2
3
40
tclk + 40
2 * tclk + 40
ns
ns
ns
8
tCDV
Propagation Delay (Note 2)
CLK Falling Edge to Serial Data Valid, SDO
CLK Rising Edge to Serial Data Valid, SDO
CLK Falling Edge to Serial Data Valid, SDO
1
2
3
40
tclk + 40
2 * tclk + 40
ns
ns
ns
Slave Mode: ISLAV = 1
Setup Time (Note 3)
SCLK to Rising Edge of CLK
9
tsu
15
ns
9
th
Hold Time (Note 3)
SCLK to Rising Edge of CLK
0
ns
9
tsclkh
tsclkl
tsu
SCLK High
20
ns
9
SCLK Low
20
ns
9
Setup Time (Note 3)
SYNC to Rising Edge of CLK
15
ns
9
th
Hold Time (Note 3)
SYNC to Rising Edge of CLK
0
ns
tCDV
Propagation Delay
Clk Rising Edge to Serial Data Valid, SDO
1
2
3
twch
tclk
tclk + twch
twch + 40
2 * tclk + 40
3 * tclk + twch + 40
NOTES:
1. The internal clock frequency, or input sampling frequency (CLKI) is governed by the divide mode and output data rate.
The divide mode can be either 1, 2, or 3. The output data rate ranges from 24 kHz to 48 kHz.
The minimum clock frequency of 3.072 MHz corresponds to an output data rate of 24 kHz with the device in the clock divide by one mode.
The maximum clock frequency of 18.432 MHz corresponds to an output data rate of 48 kHz with the device in the clock divide by three mode.
2. Propagation delay is measured with a capacitive load of 50 pF.
3. In the slave mode, SYNC or SCLK transitions can occur anywhere except 0 to – 5 ns relative to the CLK rising edge.
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