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參數(shù)資料
| 型號： | MC145073DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | Dual 16-Bit Stereo Audio Sigma-Delta ADC |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 224K |
| 代理商： | MC145073DW |
MOTOROLA
MC145073
3
ANALOG SPECIFICATIONS
(Full Temperature, CLK = 6.144 MHz in div1, VDD(A) = VDD(D) = 5.0 V, 1007.8 Hz Full–Scale Input Sinewave, 1.4 V p–p @ AIN(L) and AIN(R),
Common Mode Input Voltage = 2.5 V. Measured bandwidth is 23 Hz to 24 kHz, inputs driven differentially per Figure 1.)
Parameter
Min
Typ
Max
Unit
Resolution Bits
16
Bits
S/(N+D)
76
82
dB
Dynamic Range
85
dB
Total Harmonic Distortion (Vin =
±
F.S.)
.003
%
Gain Error
±
5
%
Gain Drift
50
ppm/
°
C
Channel to Channel Isolation
90
dB
PSRR (VDD(A))
PSRR (VDD(D))
Input Impedance
60
dB
100
dB
40
k
Warm–Up Time (for Reference and Bias Circuits)
1
ms
DIGITAL FILTER CHARACTERIZATION
(Over full operating ranges per Operating Ranges table. Stated values are for input/output relationships from input of comb filter to output of
FIR filter.)
Parameter
Output Data Rate
U i
Unit
Notes
32 kHz
44.1 kHz
48 kHz
FSEL = low
FIR Filter Passband
0 to 13.3
0 to 18.3
0 to 20
kHz
Maximum Passband Ripple
±
0.1
±
0.1
±
0.1
dB
FIR Filter Transition Band
13.3 to 17
18.3 to 23.5
20 to 25.8
kHz
FIR Filter Rejection (Min)
– 84
– 84
– 84
dB
Maximum Alias Level (Figure 3)
– 86
– 86
– 86
dB
1, 2
Group Delay
33
33
33
Out CLKS
3
Setting Time
49
49
49
Out CLKS
3
FSEL = high
FIR Filter Passband
0 to 14.5
0 to 20
0 to 21.7
kHz
Maximum Passband Ripple
±
0.1
±
0.1
±
0.1
dB
FIR Filter Transition Band
14.5 to 18.2
20 to 25.0
21.7 to 27.3
kHz
FIR Filter Rejection (Min)
– 84
– 84
– 84
dB
Maximum Alias Level (Figure 3)
– 86
– 86
– 86
dB
1, 2
Group Delay
33
33
33
Out CLKS
3
Setting Time
49
49
49
Out CLKS
3
NOTES:
1. There is no rejection of input signals that are multiples of the sampling frequency (nxCLKI
±
Filter Bandwidth, where n = 0, 1, 2, ...).
2. The maximum alias level spec does not apply to input signals in the range of 24 to 25.8 kHz in the 48 kHz output mode, 22.05 to 23.675 kHz
in the 44.1 kHz output mode, or 16 to 17.2 kHz in the 32 kHz output mode.
3. One Out CLK (output clock) is equal in length to 128 internal CLKs or one SYNC clock period.
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