參數(shù)資料
型號(hào)： MC1401A-P
廠商： Electronic Theatre Controls, Inc.
英文描述： Advanced Brushless Motor Control Chipset
中文描述： 先進(jìn)的無(wú)刷電機(jī)控制芯片組
文件頁(yè)數(shù)： 14/70頁(yè)
文件大?。?/td> 474K
代理商： MC1401A-P
14
IC
I/O
Pin Name
HostRdy
Pin #
37
Description/Functionality
Host Port Ready/Busy (output). This signal is used to synchronize communication between
the DSP and the host. HostRdy will go low (indicating host port busy) at the end of a host
command write or after the second byte of a data write or read. HostRdy will go high
(indicating host port ready) when the command or data word has been processed and the
chip set is ready for more I/O operations. All host port communications must be made with
HostRdy high (indicating ready).
Typical busy to ready cycle is 67.5 uSec, although it can be longer when host port traffic is
high.
Host Port Read data (input). Used to indicate that a data word is being read fromthe chip set
(low asserts read).
Host Port Write data (input). Used to indicate that a data word or command is being written to
the chip set (low asserts write).
Host Port Select (input). Used to select the host port for reading or writing operations (low
assertion selects port). ~HostSlct must remain inactive (high) when the host port is not in use.
Host Interrupt (output). A low assertion on this pin indicates that a host interrupt condition
exists that may require special host action.
Host Port Data 0-7 (bi-directional, tri-stated). These signals formthe 8 bit host data port used
during communication to/fromthe chip set. This port is controlled by ~HostSlct, ~HostWrite,
~HostRead and HostCmd.
I/O
~HostRead
51
I/O
~HostWrite
47
I/O
~HostSlct
48
I/O
~HostIntrpt
44
I/O
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
Hall1A
Hall1B
Hall1C
Hall2A
Hall2B
Hall2C
50
61
53
65
67
62
64
60
18
5
6
7
8
17
3
1
40
35
19
39
34
16
I/O
I/O chip to CP chip data port (bi-directional). These 8 bits are connected to the corresponding
Data4-11 pins on the CP chip, and facilitate communication to/fromthe I/O and CP chips..
I/O
Hall Sensor A, B, and C commutation inputs for axis 1 and 2 (input). Each set of the three
signals for one axis (A, B and C) encodes 6 valid signal states as follows: A on, A and B on,
B on, B and C on, C on, C and A on. An on state is defined as a high signal.
NOTE: These signals should only be connected to Hall sensors that are mounted 120-deg
offset fromeach other. Schemes which provide Hall signals 60-deg apart will not work.
NOTE: For MC1231A all 6 pins are valid. For MC1131A pins for axis 1 only are valid. Invalid
axis pins can be left unconnected.
I/O chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply
voltage = 4.75 to 5.25 V
I/O chip ground pin. All of these pins must be connected to the power supply return.
I/O
Vcc
4, 21, 25, 38, 55
I/O
GND
14, 15, 32, 49, 54,
66
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