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參數(shù)資料
| 型號(hào)： | MC14012UBCL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | UB-Suffix Series COMS Gates |
| 中文描述： | 4000/14000/40000 SERIES, DUAL 4-INPUT NAND GATE, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 321K |
| 代理商： | MC14012UBCL |
MOTOROLA CMOS LOGIC DATA
21
MC14001UB
Characteristic
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
Output Fall Time
tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns
* The formulas given are for the typical characteristics only at 25 C.
Symbol
Vdc
5.0
15
Min
—
—
Typ #
180
65
Max
360
130
Unit
ns
15
—
40
80
ns
tPLH, tPHL
15
—
40
80
ns
Figure 1. Switching Time Test Circuit and Waveforms
VDD
14
VSS
OUTPUT
CL
INPUT
*
7
PULSE
GENERATOR
20 ns
20 ns
INPUT
OUTPUT
INVERTING
tPHL
tPLH
90%
50%
10%
90%
50%
10%
tTHL
tTLH
VDD
0 V
VOH
VOL
* All unused inputs of AND, NAND gates must be
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.
MC14001UB CIRCUIT SCHEMATIC
MC14002UB CIRCUIT SCHEMATIC
(1/2 of Device Shown)
14
10
3
VDD
6
5
2
1
VSS
4
7
11
12
13
9
8
5, 12
4, 11
3, 10
2, 9
VDD
14
1, 13
VSS
7
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