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參數(shù)資料
| 型號： | MC13181 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 電源管理 |
| 英文描述： | Wireless Power Management Integrated Circuit |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | PLASTIC, QFN-24 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 211K |
| 代理商： | MC13181 |
Circuit Features
MOTOROLA
MC13181
Advance Information
15
3.6 OR Gate & Inverter
The IC incorporates a general purpose inverter and OR gate. The Q1_B input is the input to the inverter
and one of the OR gate inputs. The S_INV output will be the logical inversion of the input. The S_OR
output will be the logical OR of the inverse of Q1_B and Q2. Q2 has an internal pull-down. See Figure 3.
A truth table of this function is shown in Table 7:
Figure 3. Inverter/OR Logic Block Diagram
Both inputs feature voltage robust level shifting and a Vih may range from 1.5 V through V
CC2
.
The inverter output is referenced to V
LDO_1.85
. The OR gate output is referenced to V
CC2
.
3.7 Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect the IC and the system in the event that the
maximum junction temperature is exceeded. When activated (typical threshold is set at 150
°
C), the three
LDO regulators turn off until they are reactivated. This feature is provided to prevent failures from
inadvertent overheating. Hysteresis allows stable thermal recovery.
Care should be taken in design to ensure that regulator loading and ambient thermal conditions are
managed to avoid excessive power dissipation and thermal shutdown in normal operation.
PC board layout should include connection to exposed thermal pad on IC and ensure adequate heat
dissipation.
Table 7.
Inverter/OR Logic Truth Table
Q1_B
Q2
S_OR
S_INV
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
0
Q1_B
Q2
S_INV
S_OR
1.0 M
1.85 V
V
CC2
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