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參數資料
| 型號： | MC13155 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Wideband FM IF Detector(寬頻帶FM IF探測器) |
| 中文描述： | 寬帶調頻中頻中頻探測器探測（寬頻帶調頻） |
| 文件頁數： | 10/16頁 |
| 文件大?。?/td> | 267K |
| 代理商： | MC13155 |
MC13155
10
MOTOROLA ANALOG IC DEVICE DATA
DC Biasing Considerations
The DC biasing scheme utilizes two VCC connections
(Pins 3 and 6) and two VEE connections (Pins 14 and 11).
VEE1 (Pin 14) is connected internally to the IF and RSSI
circuits’ negative supply bus while VEE2 (Pin 11) is connected
internally to the quadrature detector’s negative bus. Under
positive ground operation, this unique configuration offers the
ability to bias the RSSI and IF separately from the quadrature
detector. When two ICs are cascaded as shown in the 70
MHz application circuit and provided by the PCB (see
Figures 17 and 18), the first MC13155 is used without biasing
its quadrature detector, thereby saving approximately 3.0
mA. A total current of 7.0 mA is used to fully bias each IC,
thus the total current in the application circuit is
approximately 11 mA. Both VCC pins are biased by the same
supply. VCC1 (Pin 3) is connected internally to the positive
bus of the first half of the IF limiting amplifier, while VCC2 is
internally connected to the positive bus of the RSSI, the
quadrature detector circuit, and the second half of the IF
limiting amplifier (see Figure 15). This distribution of the VCC
enhances the stability of the IC.
RSSI Circuitry
The RSSI circuitry provides typically 35 dB of linear
dynamic range and its output voltage swing is adjusted by
selection of the resistor from Pin 12 to VEE. The RSSI slope
is typically 2.1
μ
A/dB ; thus, for a dynamic range of 35 dB, the
current output is approximately 74
μ
A. A 47 k resistor will
yield an RSSI output voltage swing of 3.5 Vdc. The RSSI
buffer output at Pin 13 is an emitter–follower and needs an
external emitter resistor of 10 k to VEE.
In a cascaded configuration (see circuit application in
Figure 16), only one of the RSSI Buffer outputs (Pin 13) is
used; the RSSI outputs (Pin 12 of each IC) are tied together
and the one closest to the VEE supply trace is decoupled to
VCC ground. The two pins are connected to VEE through a 47
k resistor. This resistor sources a RSSI current which is
proportional to the signal level at the IF input; typically,
1.0 mVrms (– 47 dBm) is required to place the MC13155 into
limiting. The measured RSSI output voltage response of the
application circuit is shown in Figure 12. Since the RSSI
current output is dependent upon the input signal level at the
IF input, a careful accounting of filter losses, matching and
other losses and gains must be made in the entire receiver
system. In the block diagram of the application circuit shown
below, an accounting of the signal levels at points throughout
the system shows how the RSSI response in Figure 12 is
justified.
Block Diagram of 70 MHz Video Receiver Application Circuit
Input
Level:
– 45 dBm
1.26 mVrms
– 70 dBm
71
μ
Vrms
– 72 dBm
57
μ
Vrms
– 32 dBm
57
μ
Vrms
– 47 dBm
1.0 mVrms
Minimum Input to Acquire
Limiting in MC13155
MC13155
7
10
1
16
1
16
MC13155
40 dB Gain
–15 dB
(Attenuator)
40 dB Gain
1:4
Transformer
2.0 dB
(Insertion Loss)
– 25 dB
(Insertion Loss)
Saw
Filter
IF
Input
Cascading Stages
The limiting IF output is pinned–out differentially,
cascading is easily achieved by AC coupling stage to stage.
In the evaluation PCB, AC coupling is shown, however,
interstage filtering may be desirable in some applications. In
which case, the S–parameters provide a means to implement
a low loss interstage match and better receiver sensitivity.
Where a linear response of the RSSI output is desired
when cascading the ICs, it is necessary to provide at least
10 dB of interstage loss. Figure 12 shows the RSSI response
with and without interstage loss. A 15 dB resistive attenuator
is an inexpensive way to linearize the RSSI response. This
has its drawbacks since it is a wideband noise source that is
dependent upon the source and load impedance and the
amount of attenuation that it provides. A better, although
more costly, solution would be a bandpass filter designed to
the desired center frequency and bandpass response while
carefully selecting the insertion loss. A network topology
shown below may be used to provide a bandpass response
with the desired insertion loss.
1.0n
1
16
7
10
0.22
μ
1.0n
Network Topology
相關PDF資料 |
PDF描述 |
|---|---|
| MC13155D | WIDEBAND FM IF |
| MC13156 | Wideband FM IF System |
| MC13158 | WIDEBAND FM IF SUBSYSTEM FOR DECT AND DIGITAL APPLICATIONS |
| MC13181 | Wireless Power Management Integrated Circuit |
| MC13181R2 | Wireless Power Management Integrated Circuit |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC13155D | 制造商:LANSDALE 制造商全稱:LANSDALE Semiconductor Inc. 功能描述:Wideband FM IF |
| MC13156 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Wideband FM IF System |
| MC13156DW | 制造商:Motorola Inc 功能描述: |
| MC13156FB | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:WIDEBAND FM IF SYSTEM FOR DIGITAL AND ANALOG APPLICATIONS |
| MC13158 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:WIDEBAND FM IF SUBSYSTEM FOR DECT AND DIGITAL APPLICATIONS |
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