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參數(shù)資料
| 型號： | MC12210DT |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | MECL PLL COMPONENTS SERIAL PLL FREQUENCY SYNTIESIZER |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 142K |
| 代理商： | MC12210DT |
MC12210
7
MOTOROLA RF/IF DEVICE DATA
For FC = HIGH:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the
φ
P output will remain in a HIGH state while the
φ
R
output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180
°
out of phase condition.
The signal on
φ
R indicates to the VCO to decrease in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the
φ
R output will remain in a LOW state while the
φ
P
output pulses from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180
°
out of phase condition.
The signal on
φ
P indicates to the VCO to increase in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output
φ
P will remain in a HIGH state and
φ
R will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will
maintain the loop in its locked state.
When FC = LOW, the operation of the phase comparator is reversed from the above explanation.
For FC = LOW:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the
φ
R output will remain in a LOW state while the
φ
P
output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180
°
out of phase condition.
The signal on
φ
P indicates to the VCO to increase in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the
φ
P output will remain in a HIGH state while the
φ
R
output pulses from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180
°
out of phase condition.
The signal on
φ
R indicates to the VCO to decrease in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output
φ
P will remain in a HIGH state and
φ
R will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will
maintain the loop in its locked state.
The FC pin controls not only the phase characteristics, but also controls the fOUT test pin. The FC pin permits the user to monitor
either of the phase comparator input signals, fr or fp, at the fOUT output providing a test mode where the programming of the
dividers and the output of the counters can be checked. When FC is HIGH, fOUT = fr, the programmable reference divider output.
When FC is LOW, fOUT = fp, the programmable divider output.
Hence,
If VCO characteristics are like (1), FC should be set HIGH or OPEN.
If VCO characteristics are like (2), FC should be set LOW.
fOUT = fr
fOUT = fp
Figure 4. VCO Characteristics
VCO INPUT VOLTAGE
V
( 1 )
( 2 )
Figure 5. Phase Comparator, Internal Charge Pump, and
fOUT Characteristics
FC = HIGH or OPEN
FC = LOW
Do
φ
R
φ
P
fOUT
Do
φ
R
φ
P
fOUT
fp < fr
H
L
L
fr
L
H
H
fp
fp > fr
L
H
H
fr
H
L
L
fp
fp = fr
NOTES:Z = High impedance
When LE is HIGH or Open, BISW has the same
characteristics as Do.
Z
L
H
fr
Z
L
H
fp
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